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[Core/MCD] disabled CD hardware reset on Soft-Reset (verified on real hardware)

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EkeEke 2013-10-21 00:27:10 +02:00 committed by twinaphex
parent 5fbde4e187
commit cf6081fb69
2 changed files with 14 additions and 12 deletions
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5
core/cd_hw/scd.c
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@ -1218,6 +1218,11 @@ void scd_reset(int hard)
m68k.memory_map[i].base = scd.prg_ram; m68k.memory_map[i].base = scd.prg_ram;
m68k.memory_map[i+1].base = scd.prg_ram + 0x10000; m68k.memory_map[i+1].base = scd.prg_ram + 0x10000;
} }
/* reset & halt SUB-CPU */
s68k.cycles = 0;
s68k_pulse_reset();
s68k_pulse_halt();
} }
else else
{ {

13
core/genesis.c
View File

@ -252,20 +252,17 @@ void gen_reset(int hard_reset)
if ((system_hw & SYSTEM_PBC) == SYSTEM_MD) if ((system_hw & SYSTEM_PBC) == SYSTEM_MD)
{ {
if (system_hw == SYSTEM_MCD) if (system_hw == SYSTEM_MCD)
{
/* FRES is only asserted on Power ON */
if (hard_reset)
{ {
/* reset CD hardware */ /* reset CD hardware */
scd_reset(1); scd_reset(1);
/* reset & halt SUB-CPU */
s68k.cycles = 0;
s68k_pulse_reset();
s68k_pulse_halt();
} }
else }
{
/* reset MD cartridge hardware */ /* reset MD cartridge hardware */
md_cart_reset(hard_reset); md_cart_reset(hard_reset);
}
/* Z80 bus is released & Z80 is reseted */ /* Z80 bus is released & Z80 is reseted */
m68k.memory_map[0xa0].read8 = m68k_read_bus_8; m68k.memory_map[0xa0].read8 = m68k_read_bus_8;