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[Core/CD] fixed BOOT ROM level 4 interrupt vector upper word value (verified on real hardware, cf. Krikzz's mcd-verificator)

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ekeeke 2023-11-26 17:48:55 +01:00
parent 02c9dac337
commit d4ca576c07
2 changed files with 2 additions and 1 deletions
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2
HISTORY.txt
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@ -47,7 +47,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
* fixed PRG-RAM access from MAIN-CPU side on system reset * fixed PRG-RAM access from MAIN-CPU side on system reset
* fixed state loading bug when SUB-CPU interrupt is pending * fixed state loading bug when SUB-CPU interrupt is pending
* fixed H-INT vector handling when using Mode 1 * fixed H-INT vector handling when using Mode 1
* fixed H-INT vector upper word value * fixed BOOT ROM level 4 interrupt vector upper word value (verified on real hardware, cf. Krikzz's mcd-verificator)
* fixed access to "write-only" communication flags (verified on real hardware by Notaz) * fixed access to "write-only" communication flags (verified on real hardware by Notaz)
* fixed access to Sub-CPU "read-only" communication registers (fixes Round 5 Boss freeze in Streets of Rage / Sega Classics Arcade Collection) * fixed access to Sub-CPU "read-only" communication registers (fixes Round 5 Boss freeze in Streets of Rage / Sega Classics Arcade Collection)
* fixed byte access to memory mode, timer and font color registers at even address (verified on real hardware, cf. Krikzz's mcd-verificator) * fixed byte access to memory mode, timer and font color registers at even address (verified on real hardware, cf. Krikzz's mcd-verificator)

1
core/cd_hw/scd.c
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@ -1727,6 +1727,7 @@ void scd_reset(int hard)
scd.dmna = 0; scd.dmna = 0;
/* H-INT default vector */ /* H-INT default vector */
*(uint16 *)(m68k.memory_map[scd.cartridge.boot].base + 0x70) = 0xFFFF;
*(uint16 *)(m68k.memory_map[scd.cartridge.boot].base + 0x72) = 0xFFFF; *(uint16 *)(m68k.memory_map[scd.cartridge.boot].base + 0x72) = 0xFFFF;
/* Power ON initial values (MAIN-CPU side) */ /* Power ON initial values (MAIN-CPU side) */