mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-06-02 08:38:43 +02:00
[Core/CD] improved GFX processing accuracy to halt it while Word RAM is allocated to Main CPU in 2M mode
This commit is contained in:
ekeeke
parent
dded47d5e7
commit
ea8d299123
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@ -29,6 +29,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
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* improved CDD "play" command accuracy (fixes "Snatcher" Act 2 starting cutscene)
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* improved CDD status report accuracy (fixes track looping with Mode 1 patched games using MSU-MD driver)
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* improved Word-RAM byte access accuracy (verified on schematics)
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* improved GFX processing accuracy to halt it while Word RAM is allocated to Main CPU in 2M mode
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* disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes "Dungeon Explorer")
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* disabled CD hardware reset on Soft-Reset (verified on real hardware)
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* fixed potential load issues with non-zero backup RAM cart
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213
core/cd_hw/gfx.c
213
core/cd_hw/gfx.c
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@ -586,132 +586,137 @@ INLINE void gfx_render(uint32 bufferIndex, uint32 width)
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void gfx_start(unsigned int base, int cycles)
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{
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/* make sure 2M mode is enabled */
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if (!(scd.regs[0x02>>1].byte.l & 0x04))
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uint32 mask;
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/* trace vector pointer */
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gfx.tracePtr = (uint16 *)(scd.word_ram_2M + ((base << 2) & 0x3fff8));
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/* stamps & stamp map size */
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switch ((scd.regs[0x58>>1].byte.l >> 1) & 0x03)
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{
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uint32 mask;
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/* trace vector pointer */
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gfx.tracePtr = (uint16 *)(scd.word_ram_2M + ((base << 2) & 0x3fff8));
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case 0:
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gfx.dotMask = 0x07ffff; /* 256x256 dots/map */
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gfx.stampShift = 11 + 4; /* 16x16 dots/stamps */
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gfx.mapShift = 4; /* 16x16 stamps/map */
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mask = 0x3fe00; /* 512 bytes/table */
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break;
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/* stamps & stamp map size */
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switch ((scd.regs[0x58>>1].byte.l >> 1) & 0x03)
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{
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case 0:
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gfx.dotMask = 0x07ffff; /* 256x256 dots/map */
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gfx.stampShift = 11 + 4; /* 16x16 dots/stamps */
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gfx.mapShift = 4; /* 16x16 stamps/map */
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mask = 0x3fe00; /* 512 bytes/table */
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break;
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case 1:
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gfx.dotMask = 0x07ffff; /* 256x256 dots/map */
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gfx.stampShift = 11 + 5; /* 32x32 dots/stamps */
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gfx.mapShift = 3; /* 8x8 stamps/map */
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mask = 0x3ff80; /* 128 bytes/table */
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break;
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case 1:
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gfx.dotMask = 0x07ffff; /* 256x256 dots/map */
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gfx.stampShift = 11 + 5; /* 32x32 dots/stamps */
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gfx.mapShift = 3; /* 8x8 stamps/map */
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mask = 0x3ff80; /* 128 bytes/table */
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break;
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case 2:
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gfx.dotMask = 0x7fffff; /* 4096*4096 dots/map */
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gfx.stampShift = 11 + 4; /* 16x16 dots/stamps */
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gfx.mapShift = 8; /* 256x256 stamps/map */
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mask = 0x20000; /* 131072 bytes/table */
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break;
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case 2:
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gfx.dotMask = 0x7fffff; /* 4096*4096 dots/map */
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gfx.stampShift = 11 + 4; /* 16x16 dots/stamps */
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gfx.mapShift = 8; /* 256x256 stamps/map */
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mask = 0x20000; /* 131072 bytes/table */
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break;
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case 3:
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gfx.dotMask = 0x7fffff; /* 4096*4096 dots/map */
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gfx.stampShift = 11 + 5; /* 32x32 dots/stamps */
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gfx.mapShift = 7; /* 128x128 stamps/map */
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mask = 0x38000; /* 32768 bytes/table */
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break;
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}
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/* stamp map table base address */
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gfx.mapPtr = (uint16 *)(scd.word_ram_2M + ((scd.regs[0x5a>>1].w << 2) & mask));
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/* image buffer column offset (64 pixels/cell, minus 7 pixels to restart at cell beginning) */
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gfx.bufferOffset = (((scd.regs[0x5c>>1].byte.l & 0x1f) + 1) << 6) - 7;
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/* image buffer start index in dot units (2 pixels/byte) */
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gfx.bufferStart = (scd.regs[0x5e>>1].w << 3) & 0x7ffc0;
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/* add image buffer horizontal dot offset */
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gfx.bufferStart += (scd.regs[0x60>>1].byte.l & 0x3f);
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/* reset GFX chip cycle counter */
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gfx.cycles = cycles;
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/* update GFX chip timings (see AC3:Thunderhawk / Thunderstrike) */
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gfx.cyclesPerLine = 4 * 5 * scd.regs[0x62>>1].w;
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/* start graphics operation */
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scd.regs[0x58>>1].byte.h = 0x80;
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case 3:
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gfx.dotMask = 0x7fffff; /* 4096*4096 dots/map */
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gfx.stampShift = 11 + 5; /* 32x32 dots/stamps */
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gfx.mapShift = 7; /* 128x128 stamps/map */
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mask = 0x38000; /* 32768 bytes/table */
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break;
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}
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/* stamp map table base address */
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gfx.mapPtr = (uint16 *)(scd.word_ram_2M + ((scd.regs[0x5a>>1].w << 2) & mask));
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/* image buffer column offset (64 pixels/cell, minus 7 pixels to restart at cell beginning) */
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gfx.bufferOffset = (((scd.regs[0x5c>>1].byte.l & 0x1f) + 1) << 6) - 7;
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/* image buffer start index in dot units (2 pixels/byte) */
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gfx.bufferStart = (scd.regs[0x5e>>1].w << 3) & 0x7ffc0;
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/* add image buffer horizontal dot offset */
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gfx.bufferStart += (scd.regs[0x60>>1].byte.l & 0x3f);
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/* reset GFX chip cycle counter */
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gfx.cycles = cycles;
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/* update GFX chip timings (see AC3:Thunderhawk / Thunderstrike) */
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gfx.cyclesPerLine = 4 * 5 * scd.regs[0x62>>1].w;
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/* start graphics operation */
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scd.regs[0x58>>1].byte.h = 0x80;
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}
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void gfx_update(int cycles)
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{
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/* synchronize GFX chip with SUB-CPU */
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cycles -= gfx.cycles;
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/* make sure SUB-CPU is ahead */
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if (cycles > 0)
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/* make sure Word-RAM is assigned to SUB-CPU in 2M mode */
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if ((scd.regs[0x02>>1].byte.l & 0x05) != 0x01)
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{
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/* number of lines to process */
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unsigned int lines = (cycles + gfx.cyclesPerLine - 1) / gfx.cyclesPerLine;
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/* synchronize GFX processing with SUB-CPU */
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cycles -= gfx.cycles;
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/* check against remaining lines */
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if (lines < scd.regs[0x64>>1].byte.l)
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/* make sure SUB-CPU is ahead */
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if (cycles > 0)
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{
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/* update Vdot remaining size */
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scd.regs[0x64>>1].byte.l -= lines;
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/* number of lines to process */
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unsigned int lines = (cycles + gfx.cyclesPerLine - 1) / gfx.cyclesPerLine;
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/* increment cycle counter */
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gfx.cycles += lines * gfx.cyclesPerLine;
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}
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else
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{
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/* process remaining lines */
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lines = scd.regs[0x64>>1].byte.l;
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/* clear Vdot remaining size */
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scd.regs[0x64>>1].byte.l = 0;
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/* end of graphics operation */
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scd.regs[0x58>>1].byte.h = 0;
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/* SUB-CPU idle on register $58 polling ? */
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if (s68k.stopped & (1<<0x08))
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/* check against remaining lines */
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if (lines < scd.regs[0x64>>1].byte.l)
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{
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/* sync SUB-CPU with GFX chip */
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s68k.cycles = scd.cycles;
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/* update Vdot remaining size */
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scd.regs[0x64>>1].byte.l -= lines;
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/* restart SUB-CPU */
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s68k.stopped = 0;
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/* increment cycle counter */
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gfx.cycles += lines * gfx.cyclesPerLine;
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}
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else
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{
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/* process remaining lines */
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lines = scd.regs[0x64>>1].byte.l;
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/* clear Vdot remaining size */
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scd.regs[0x64>>1].byte.l = 0;
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/* end of graphics operation */
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scd.regs[0x58>>1].byte.h = 0;
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/* SUB-CPU idle on register $58 polling ? */
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if (s68k.stopped & (1<<0x08))
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{
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/* sync SUB-CPU with GFX chip */
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s68k.cycles = scd.cycles;
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/* restart SUB-CPU */
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s68k.stopped = 0;
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#ifdef LOG_SCD
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error("s68k started from %d cycles\n", s68k.cycles);
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error("s68k started from %d cycles\n", s68k.cycles);
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#endif
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}
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/* level 1 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x02)
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{
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/* trigger level 1 interrupt */
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scd.pending |= (1 << 1);
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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}
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/* level 1 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x02)
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/* render lines */
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while (lines--)
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{
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/* trigger level 1 interrupt */
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scd.pending |= (1 << 1);
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/* process dots to image buffer */
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gfx_render(gfx.bufferStart, scd.regs[0x62>>1].w);
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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/* increment image buffer start index for next line (8 pixels/line) */
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gfx.bufferStart += 8;
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}
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}
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/* render lines */
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while (lines--)
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{
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/* process dots to image buffer */
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gfx_render(gfx.bufferStart, scd.regs[0x62>>1].w);
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/* increment image buffer start index for next line (8 pixels/line) */
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gfx.bufferStart += 8;
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}
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}
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else
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{
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/* GFX processing is halted */
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gfx.cycles = cycles;
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}
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}
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@ -932,6 +932,13 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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/* RET bit set in 2M mode */
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if (data & 0x01)
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{
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/* check if graphics operation is running */
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if (scd.regs[0x58>>1].byte.h & 0x80)
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{
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/* synchronize GFX processing with SUB-CPU */
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gfx_update(s68k.cycles);
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}
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/* Word-RAM is returned to MAIN-CPU */
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scd.dmna = 0;
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@ -1196,6 +1203,13 @@ static void scd_write_word(unsigned int address, unsigned int data)
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/* RET bit set in 2M mode */
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if (data & 0x01)
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{
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/* check if graphics operation is running */
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if (scd.regs[0x58>>1].byte.h & 0x80)
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{
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/* synchronize GFX processing with SUB-CPU */
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gfx_update(s68k.cycles);
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}
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/* Word-RAM is returned to MAIN-CPU */
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scd.dmna = 0;
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@ -3,7 +3,7 @@
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* Main 68k bus handlers
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*
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 2007-2022 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -777,7 +777,7 @@ void ctrl_io_write_byte(unsigned int address, unsigned int data)
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}
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else
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{
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/* writing 0 to DMNA in 1M mode actually set DMNA bit */
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/* writing 0 to DMNA in 1M mode actually sets DMNA bit */
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data |= 0x02;
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/* update BK0-1 & DMNA bits */
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@ -787,19 +787,32 @@ void ctrl_io_write_byte(unsigned int address, unsigned int data)
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}
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else
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{
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/* writing 0 in 2M mode does nothing */
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/* writing 0 to DMNA in 2M mode does nothing */
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if (data & 0x02)
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{
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/* Word-RAM is assigned to SUB-CPU */
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scd.dmna = 1;
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/* clear RET bit */
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/* clear RET bit and update BK0-1 & DMNA bits */
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scd.regs[0x03>>1].byte.l = (scd.regs[0x03>>1].byte.l & ~0xc3) | (data & 0xc2);
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/* check if graphics operation is running */
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if (scd.regs[0x58>>1].byte.h & 0x80)
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{
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/* relative SUB-CPU cycle counter */
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unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
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/* synchronize GFX processing with SUB-CPU (only if not already ahead) */
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if (gfx.cycles < cycles)
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{
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gfx.cycles = cycles;
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}
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}
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return;
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}
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}
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/* update BK0-1 bits */
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/* update BK0-1 bits only */
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scd.regs[0x03>>1].byte.l = (scd.regs[0x02>>1].byte.l & ~0xc0) | (data & 0xc0);
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return;
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}
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@ -1014,7 +1027,7 @@ void ctrl_io_write_word(unsigned int address, unsigned int data)
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}
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else
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{
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/* writing 0 to DMNA in 1M mode actually set DMNA bit */
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/* writing 0 to DMNA in 1M mode actually sets DMNA bit */
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data |= 0x02;
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/* update WP0-7, BK0-1 & DMNA bits */
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@ -1024,19 +1037,32 @@ void ctrl_io_write_word(unsigned int address, unsigned int data)
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}
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else
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{
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/* writing 0 in 2M mode does nothing */
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/* writing 0 to DMNA in 2M mode does nothing */
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if (data & 0x02)
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{
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/* Word-RAM is assigned to SUB-CPU */
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scd.dmna = 1;
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/* clear RET bit */
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/* clear RET bit and update WP0-7 & BK0-1 bits */
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scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc3) | (data & 0xffc2);
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/* check if graphics operation is running */
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if (scd.regs[0x58>>1].byte.h & 0x80)
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{
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/* relative SUB-CPU cycle counter */
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unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
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/* synchronize GFX processing with SUB-CPU (only if not already ahead) */
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if (gfx.cycles < cycles)
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{
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gfx.cycles = cycles;
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}
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}
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return;
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}
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}
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/* update WP0-7 & BK0-1 bits */
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/* update WP0-7 & BK0-1 bits only */
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scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc0) | (data & 0xffc0);
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return;
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}
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@ -3,7 +3,7 @@
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* Main 68k bus handlers
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*
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 2007-2022 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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