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[Core/CD] improved GFX processing accuracy to halt it while Word RAM is allocated to Main CPU in 2M mode

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This commit is contained in:
ekeeke 2022-10-09 10:13:24 +02:00
parent dded47d5e7
commit ea8d299123
5 changed files with 160 additions and 114 deletions
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1
HISTORY.txt
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@ -29,6 +29,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
* improved CDD "play" command accuracy (fixes "Snatcher" Act 2 starting cutscene) * improved CDD "play" command accuracy (fixes "Snatcher" Act 2 starting cutscene)
* improved CDD status report accuracy (fixes track looping with Mode 1 patched games using MSU-MD driver) * improved CDD status report accuracy (fixes track looping with Mode 1 patched games using MSU-MD driver)
* improved Word-RAM byte access accuracy (verified on schematics) * improved Word-RAM byte access accuracy (verified on schematics)
* improved GFX processing accuracy to halt it while Word RAM is allocated to Main CPU in 2M mode
* disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes "Dungeon Explorer") * disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes "Dungeon Explorer")
* disabled CD hardware reset on Soft-Reset (verified on real hardware) * disabled CD hardware reset on Soft-Reset (verified on real hardware)
* fixed potential load issues with non-zero backup RAM cart * fixed potential load issues with non-zero backup RAM cart

15
core/cd_hw/gfx.c
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@ -586,9 +586,6 @@ INLINE void gfx_render(uint32 bufferIndex, uint32 width)
void gfx_start(unsigned int base, int cycles) void gfx_start(unsigned int base, int cycles)
{ {
/* make sure 2M mode is enabled */
if (!(scd.regs[0x02>>1].byte.l & 0x04))
{
uint32 mask; uint32 mask;
/* trace vector pointer */ /* trace vector pointer */
@ -646,12 +643,14 @@ void gfx_start(unsigned int base, int cycles)
/* start graphics operation */ /* start graphics operation */
scd.regs[0x58>>1].byte.h = 0x80; scd.regs[0x58>>1].byte.h = 0x80;
}
} }
void gfx_update(int cycles) void gfx_update(int cycles)
{ {
/* synchronize GFX chip with SUB-CPU */ /* make sure Word-RAM is assigned to SUB-CPU in 2M mode */
if ((scd.regs[0x02>>1].byte.l & 0x05) != 0x01)
{
/* synchronize GFX processing with SUB-CPU */
cycles -= gfx.cycles; cycles -= gfx.cycles;
/* make sure SUB-CPU is ahead */ /* make sure SUB-CPU is ahead */
@ -714,4 +713,10 @@ void gfx_update(int cycles)
gfx.bufferStart += 8; gfx.bufferStart += 8;
} }
} }
}
else
{
/* GFX processing is halted */
gfx.cycles = cycles;
}
} }

14
core/cd_hw/scd.c
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@ -932,6 +932,13 @@ static void scd_write_byte(unsigned int address, unsigned int data)
/* RET bit set in 2M mode */ /* RET bit set in 2M mode */
if (data & 0x01) if (data & 0x01)
{ {
/* check if graphics operation is running */
if (scd.regs[0x58>>1].byte.h & 0x80)
{
/* synchronize GFX processing with SUB-CPU */
gfx_update(s68k.cycles);
}
/* Word-RAM is returned to MAIN-CPU */ /* Word-RAM is returned to MAIN-CPU */
scd.dmna = 0; scd.dmna = 0;
@ -1196,6 +1203,13 @@ static void scd_write_word(unsigned int address, unsigned int data)
/* RET bit set in 2M mode */ /* RET bit set in 2M mode */
if (data & 0x01) if (data & 0x01)
{ {
/* check if graphics operation is running */
if (scd.regs[0x58>>1].byte.h & 0x80)
{
/* synchronize GFX processing with SUB-CPU */
gfx_update(s68k.cycles);
}
/* Word-RAM is returned to MAIN-CPU */ /* Word-RAM is returned to MAIN-CPU */
scd.dmna = 0; scd.dmna = 0;

44
core/mem68k.c
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@ -3,7 +3,7 @@
* Main 68k bus handlers * Main 68k bus handlers
* *
* Copyright (C) 1998-2003 Charles Mac Donald (original code) * Copyright (C) 1998-2003 Charles Mac Donald (original code)
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX) * Copyright (C) 2007-2022 Eke-Eke (Genesis Plus GX)
* *
* Redistribution and use of this code or any derivative works are permitted * Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met: * provided that the following conditions are met:
@ -777,7 +777,7 @@ void ctrl_io_write_byte(unsigned int address, unsigned int data)
} }
else else
{ {
/* writing 0 to DMNA in 1M mode actually set DMNA bit */ /* writing 0 to DMNA in 1M mode actually sets DMNA bit */
data |= 0x02; data |= 0x02;
/* update BK0-1 & DMNA bits */ /* update BK0-1 & DMNA bits */
@ -787,19 +787,32 @@ void ctrl_io_write_byte(unsigned int address, unsigned int data)
} }
else else
{ {
/* writing 0 in 2M mode does nothing */ /* writing 0 to DMNA in 2M mode does nothing */
if (data & 0x02) if (data & 0x02)
{ {
/* Word-RAM is assigned to SUB-CPU */ /* Word-RAM is assigned to SUB-CPU */
scd.dmna = 1; scd.dmna = 1;
/* clear RET bit */ /* clear RET bit and update BK0-1 & DMNA bits */
scd.regs[0x03>>1].byte.l = (scd.regs[0x03>>1].byte.l & ~0xc3) | (data & 0xc2); scd.regs[0x03>>1].byte.l = (scd.regs[0x03>>1].byte.l & ~0xc3) | (data & 0xc2);
/* check if graphics operation is running */
if (scd.regs[0x58>>1].byte.h & 0x80)
{
/* relative SUB-CPU cycle counter */
unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
/* synchronize GFX processing with SUB-CPU (only if not already ahead) */
if (gfx.cycles < cycles)
{
gfx.cycles = cycles;
}
}
return; return;
} }
} }
/* update BK0-1 bits */ /* update BK0-1 bits only */
scd.regs[0x03>>1].byte.l = (scd.regs[0x02>>1].byte.l & ~0xc0) | (data & 0xc0); scd.regs[0x03>>1].byte.l = (scd.regs[0x02>>1].byte.l & ~0xc0) | (data & 0xc0);
return; return;
} }
@ -1014,7 +1027,7 @@ void ctrl_io_write_word(unsigned int address, unsigned int data)
} }
else else
{ {
/* writing 0 to DMNA in 1M mode actually set DMNA bit */ /* writing 0 to DMNA in 1M mode actually sets DMNA bit */
data |= 0x02; data |= 0x02;
/* update WP0-7, BK0-1 & DMNA bits */ /* update WP0-7, BK0-1 & DMNA bits */
@ -1024,19 +1037,32 @@ void ctrl_io_write_word(unsigned int address, unsigned int data)
} }
else else
{ {
/* writing 0 in 2M mode does nothing */ /* writing 0 to DMNA in 2M mode does nothing */
if (data & 0x02) if (data & 0x02)
{ {
/* Word-RAM is assigned to SUB-CPU */ /* Word-RAM is assigned to SUB-CPU */
scd.dmna = 1; scd.dmna = 1;
/* clear RET bit */ /* clear RET bit and update WP0-7 & BK0-1 bits */
scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc3) | (data & 0xffc2); scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc3) | (data & 0xffc2);
/* check if graphics operation is running */
if (scd.regs[0x58>>1].byte.h & 0x80)
{
/* relative SUB-CPU cycle counter */
unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
/* synchronize GFX processing with SUB-CPU (only if not already ahead) */
if (gfx.cycles < cycles)
{
gfx.cycles = cycles;
}
}
return; return;
} }
} }
/* update WP0-7 & BK0-1 bits */ /* update WP0-7 & BK0-1 bits only */
scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc0) | (data & 0xffc0); scd.regs[0x02>>1].w = (scd.regs[0x02>>1].w & ~0xffc0) | (data & 0xffc0);
return; return;
} }

2
core/mem68k.h
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@ -3,7 +3,7 @@
* Main 68k bus handlers * Main 68k bus handlers
* *
* Copyright (C) 1998-2003 Charles Mac Donald (original code) * Copyright (C) 1998-2003 Charles Mac Donald (original code)
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX) * Copyright (C) 2007-2022 Eke-Eke (Genesis Plus GX)
* *
* Redistribution and use of this code or any derivative works are permitted * Redistribution and use of this code or any derivative works are permitted
* provided that the following conditions are met: * provided that the following conditions are met: