9 Commits

Author	SHA1	Message	Date
ekeeke	70cfbd909f	[Core/CPU] ... - fixed 68k timings of BCHG, BCLR, BTST Dn,#Imm and Dn,Dm instructions when bit number is less than 16 (cf. Yacht.txt) - fixed 68k timings of CHK, TRAP, TRAPV, LINEA and LINEF exceptions (cf. Yacht.txt)	2023-01-06 09:03:30 +01:00
ekeeke	299724791e	[Core/CPU] fixed 68k timings of ANDI.L #Imm,Dn, ADDQ.W #Imm,An and TAS instructions (cf. Yacht.txt) + corrected typo in BTST Dn,#Imm instruction timings on SUB-CPU side	2020-08-15 00:29:20 +02:00
ekeeke	48e3321261	[Core/CPU] fixed sub 68K DIVU instruction timings	2019-11-25 17:17:26 +01:00
ekeeke	c953707ef5	[Core/CPU] fixed M68K STOP instruction edge case (case where STOP instruction unmasks pending interrupt)	2019-03-23 13:46:23 +01:00
ekeeke	50dfa94a67	[Core/CPU] fixed 68k timing of BTST Dn,#Imm instruction (verified by Flamewing in original microcode)	2019-01-09 01:08:28 +01:00
ekeeke	3fc3a57b26	[Core/68k] fixed NBCD insruction when using register operand	2017-09-25 01:09:09 +02:00
EkeEke	5a74df31ee	[Core/CPU] fixed 68k undocumented behaviors for ABCD/SBCD/NBCD instructions (thanks to flamewing for his test ROM)	2017-03-30 15:02:15 +02:00
EkeEke	2236072ce9	[Core/MCD] improved Main-CPU & Sub-CPU idle loop detection (fixes "Super League CD")	2013-10-21 00:09:50 +02:00
EkeEke	aede1b9299	rearranged core & back-end specific code (part 2)	2013-06-17 22:31:31 +02:00