4 Commits

Author	SHA1	Message	Date
ekeeke	70cfbd909f	[Core/CPU] ... - fixed 68k timings of BCHG, BCLR, BTST Dn,#Imm and Dn,Dm instructions when bit number is less than 16 (cf. Yacht.txt) - fixed 68k timings of CHK, TRAP, TRAPV, LINEA and LINEF exceptions (cf. Yacht.txt)	2023-01-06 09:03:30 +01:00
ekeeke	299724791e	[Core/CPU] fixed 68k timings of ANDI.L #Imm,Dn, ADDQ.W #Imm,An and TAS instructions (cf. Yacht.txt) + corrected typo in BTST Dn,#Imm instruction timings on SUB-CPU side	2020-08-15 00:29:20 +02:00
ekeeke	50dfa94a67	[Core/CPU] fixed 68k timing of BTST Dn,#Imm instruction (verified by Flamewing in original microcode)	2019-01-09 01:08:28 +01:00
EkeEke	aede1b9299	rearranged core & back-end specific code (part 2)	2013-06-17 22:31:31 +02:00