803 lines
19 KiB
C
803 lines
19 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Z80 bus handlers (Genesis & Master System modes)
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*
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* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
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*
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2024 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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*
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* - Redistributions may not be sold, nor may they be used in a commercial
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* product or activity.
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*
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* - Redistributions that are modified from the original source must include the
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* complete source code, including the source code for all components used by a
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* binary built from the modified sources. However, as a special exception, the
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* source code distributed need not include anything that is normally distributed
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* (in either source or binary form) with the major components (compiler, kernel,
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* and so on) of the operating system on which the executable runs, unless that
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* component itself accompanies the executable.
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*
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* - Redistributions must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#include "shared.h"
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/*--------------------------------------------------------------------------*/
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/* Handlers for access to unused addresses and those which make the */
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/* machine lock up. */
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/*--------------------------------------------------------------------------*/
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INLINE void z80_unused_w(unsigned int address, unsigned char data)
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{
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#ifdef LOGERROR
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error("Z80 unused write %04X = %02X (%x)\n", address, data, Z80.pc.w.l);
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#endif
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}
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INLINE unsigned char z80_unused_r(unsigned int address)
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{
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#ifdef LOGERROR
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error("Z80 unused read %04X (%x)\n", address, Z80.pc.w.l);
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#endif
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return 0xFF;
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}
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INLINE void z80_lockup_w(unsigned int address, unsigned char data)
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{
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#ifdef LOGERROR
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error("Z80 lockup write %04X = %02X (%x)\n", address, data, Z80.pc.w.l);
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#endif
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if (!config.force_dtack)
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{
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Z80.cycles = 0xFFFFFFFF;
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zstate = 0;
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}
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}
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INLINE unsigned char z80_lockup_r(unsigned int address)
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{
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#ifdef LOGERROR
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error("Z80 lockup read %04X (%x)\n", address, Z80.pc.w.l);
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#endif
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if (!config.force_dtack)
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{
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Z80.cycles = 0xFFFFFFFF;
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zstate = 0;
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}
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return 0xFF;
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}
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/*--------------------------------------------------------------------------*/
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/* Z80 Memory handlers (Genesis mode) */
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/*--------------------------------------------------------------------------*/
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static void z80_request_68k_bus_access(void)
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{
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/* check if 68k bus is accessed by VDP DMA */
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if ((Z80.cycles < dma_endCycles) && (dma_type < 2))
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{
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/* force Z80 to wait until end of DMA */
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Z80.cycles = dma_endCycles;
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/* check if DMA is not finished at the end of current timeframe */
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if (dma_length)
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{
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/* indicate Z80 will still be waiting for 68k bus at the end of current DMA timeframe */
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zstate |= 4;
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}
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}
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/* approximate 68k wait-states during Z80 access to 68k bus (cf https://docs.google.com/document/d/1ST9GbFfPnIjLT5loytFCm3pB0kWQ1Oe34DCBBV8saY8) */
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/* value is adjusted to get ride of graphical glitches in Rick Dangerous 2 title screen when bus refresh delays are also emulated and still get */
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/* "M68K DELAY ON Z80 ROM READ" test "passed" in Ti_'s test ROM (misc_test.bin), although the measured delay value is still slightly too high. */
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m68k.cycles += ((Z80.cycles % 7) + 68);
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/* average Z80 wait-states when accessing 68k bus (cf https://docs.google.com/document/d/1ST9GbFfPnIjLT5loytFCm3pB0kWQ1Oe34DCBBV8saY8) */
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Z80.cycles += (3 * 15);
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}
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unsigned char z80_memory_r(unsigned int address)
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{
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switch((address >> 13) & 7)
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{
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case 0: /* $0000-$3FFF: Z80 RAM (8K mirrored) */
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case 1:
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{
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return zram[address & 0x1FFF];
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}
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case 2: /* $4000-$5FFF: YM2612 */
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{
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return fm_read(Z80.cycles, address & 3);
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}
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case 3: /* $7F00-$7FFF: VDP */
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{
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if ((address >> 8) == 0x7F)
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{
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/* request access to 68k bus */
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z80_request_68k_bus_access();
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/* read from $C00000-$C0FFFF area */
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return (*zbank_memory_map[0xc0].read)(address);
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}
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return z80_unused_r(address);
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}
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default: /* $8000-$FFFF: 68k bank (32K) */
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{
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/* request access to 68k bus */
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z80_request_68k_bus_access();
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/* read from 68k banked area */
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address = zbank | (address & 0x7FFF);
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if (zbank_memory_map[address >> 16].read)
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{
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return (*zbank_memory_map[address >> 16].read)(address);
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}
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return READ_BYTE(m68k.memory_map[address >> 16].base, address & 0xFFFF);
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}
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}
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}
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void z80_memory_w(unsigned int address, unsigned char data)
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{
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switch((address >> 13) & 7)
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{
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case 0: /* $0000-$3FFF: Z80 RAM (8K mirrored) */
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case 1:
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{
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zram[address & 0x1FFF] = data;
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return;
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}
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case 2: /* $4000-$5FFF: YM2612 */
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{
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fm_write(Z80.cycles, address & 3, data);
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return;
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}
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case 3: /* Bank register and VDP */
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{
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switch(address >> 8)
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{
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case 0x60: /* $6000-$60FF: Bank register */
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{
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gen_zbank_w(data & 1);
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return;
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}
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case 0x7F: /* $7F00-$7FFF: VDP */
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{
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/* request access to 68k bus */
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z80_request_68k_bus_access();
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/* write to $C00000-$C0FFFF area */
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(*zbank_memory_map[0xc0].write)(address, data);
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return;
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}
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default:
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{
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z80_unused_w(address, data);
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return;
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}
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}
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}
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default: /* $8000-$FFFF: 68k bank (32K) */
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{
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/* request access to 68k bus */
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z80_request_68k_bus_access();
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/* write to 68k banked area */
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address = zbank | (address & 0x7FFF);
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if (zbank_memory_map[address >> 16].write)
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{
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(*zbank_memory_map[address >> 16].write)(address, data);
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return;
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}
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WRITE_BYTE(m68k.memory_map[address >> 16].base, address & 0xFFFF, data);
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return;
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}
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}
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}
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/*--------------------------------------------------------------------------*/
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/* Unused Port handlers */
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/* */
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/* Ports are unused when not in Mark III compatibility mode. */
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/* */
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/* Genesis games that access ports anyway: */
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/* Thunder Force IV reads port $BF in it's interrupt handler. */
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/* */
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/*--------------------------------------------------------------------------*/
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unsigned char z80_unused_port_r(unsigned int port)
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{
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#if LOGERROR
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error("Z80 unused read from port %04X (%x)\n", port, Z80.pc.w.l);
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#endif
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if (system_hw == SYSTEM_SMS)
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{
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unsigned int address = (Z80.pc.w.l - 1) & 0xFFFF;
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return z80_readmap[address >> 10][address & 0x3FF];
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}
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return 0xFF;
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}
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void z80_unused_port_w(unsigned int port, unsigned char data)
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{
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#if LOGERROR
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error("Z80 unused write to port %04X = %02X (%x)\n", port, data, Z80.pc.w.l);
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#endif
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}
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/*--------------------------------------------------------------------------*/
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/* MegaDrive / Genesis port handlers (Master System compatibility mode) */
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/*--------------------------------------------------------------------------*/
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void z80_md_port_w(unsigned int port, unsigned char data)
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{
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switch (port & 0xC1)
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{
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case 0x01:
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{
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io_z80_write(1, data, Z80.cycles + PBC_CYCLE_OFFSET);
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return;
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}
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case 0x40:
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case 0x41:
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{
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psg_write(Z80.cycles, data);
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return;
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}
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case 0x80:
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{
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vdp_z80_data_w(data);
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return;
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}
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case 0x81:
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{
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vdp_z80_ctrl_w(data);
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return;
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}
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default:
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{
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port &= 0xFF;
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/* write FM chip if enabled */
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if ((port >= 0xF0) && (config.ym2413 & 1))
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{
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fm_write(Z80.cycles, port, data);
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return;
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}
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z80_unused_port_w(port, data);
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return;
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}
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}
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}
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unsigned char z80_md_port_r(unsigned int port)
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{
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switch (port & 0xC1)
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{
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case 0x40:
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{
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return ((vdp_hvc_r(Z80.cycles - 15) >> 8) & 0xFF);
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}
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case 0x41:
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{
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return (vdp_hvc_r(Z80.cycles - 15) & 0xFF);
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}
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case 0x80:
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{
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return vdp_z80_data_r();
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}
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case 0x81:
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{
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return vdp_z80_ctrl_r(Z80.cycles);
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}
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default:
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{
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port &= 0xFF;
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if ((port == 0xC0) || (port == 0xC1) || (port == 0xDC) || (port == 0xDD))
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{
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return io_z80_read(port & 1);
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}
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/* read FM chip if enabled */
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if ((port >= 0xF0) && (config.ym2413 & 1))
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{
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return fm_read(Z80.cycles, port);
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}
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return z80_unused_port_r(port);
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}
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}
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}
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/*--------------------------------------------------------------------------*/
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/* Game Gear port handlers */
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/*--------------------------------------------------------------------------*/
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void z80_gg_port_w(unsigned int port, unsigned char data)
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{
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switch(port & 0xC1)
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{
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case 0x00:
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case 0x01:
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{
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port &= 0xFF;
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if (port < 0x07)
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{
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if (system_hw == SYSTEM_GG)
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{
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io_gg_write(port, data);
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return;
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}
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}
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/* full address range is decoded by Game Gear I/O chip (fixes G-LOC Air Battle) */
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else if ((port == 0x3E) || (port == 0x3F))
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{
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io_z80_write(port & 1, data, Z80.cycles + SMS_CYCLE_OFFSET);
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return;
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}
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z80_unused_port_w(port, data);
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return;
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}
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case 0x40:
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case 0x41:
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{
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psg_write(Z80.cycles, data);
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return;
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}
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case 0x80:
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{
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vdp_z80_data_w(data);
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return;
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}
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case 0x81:
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{
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vdp_sms_ctrl_w(data);
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return;
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}
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default:
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{
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z80_unused_port_w(port & 0xFF, data);
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return;
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}
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}
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}
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unsigned char z80_gg_port_r(unsigned int port)
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{
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switch(port & 0xC1)
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{
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case 0x00:
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case 0x01:
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{
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port &= 0xFF;
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if (port < 0x07)
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{
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if (system_hw == SYSTEM_GG)
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{
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return io_gg_read(port);
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}
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}
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return z80_unused_port_r(port);
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}
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case 0x40:
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{
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return ((vdp_hvc_r(Z80.cycles) >> 8) & 0xFF);
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}
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case 0x41:
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{
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return (vdp_hvc_r(Z80.cycles) & 0xFF);
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}
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case 0x80:
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{
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return vdp_z80_data_r();
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}
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case 0x81:
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{
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return vdp_z80_ctrl_r(Z80.cycles);
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}
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default:
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{
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port &= 0xFF;
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/* full address range is decoded by Game Gear I/O chip */
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if ((port == 0xC0) || (port == 0xC1) || (port == 0xDC) || (port == 0xDD))
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{
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return io_z80_read(port & 1);
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}
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return z80_unused_port_r(port);
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}
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}
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}
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/*--------------------------------------------------------------------------*/
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/* Master System port handlers */
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/*--------------------------------------------------------------------------*/
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void z80_ms_port_w(unsigned int port, unsigned char data)
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{
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switch (port & 0xC1)
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{
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case 0x00:
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case 0x01:
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{
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/* full address range is decoded by 315-5297 I/O chip (fixes Super Tetris / Power Boggle Boggle) */
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if ((region_code != REGION_JAPAN_NTSC) || ((port & 0xFE) == 0x3E))
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{
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io_z80_write(port & 1, data, Z80.cycles + SMS_CYCLE_OFFSET);
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return;
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}
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z80_unused_port_w(port & 0xFF, data);
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return;
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}
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case 0x40:
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case 0x41:
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{
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psg_write(Z80.cycles, data);
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return;
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}
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case 0x80:
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{
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vdp_z80_data_w(data);
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return;
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}
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case 0x81:
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{
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vdp_sms_ctrl_w(data);
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return;
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}
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default:
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{
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/* check if YM2413 chip is enabled */
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if (config.ym2413 & 1)
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{
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if (region_code == REGION_JAPAN_NTSC)
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{
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/* 315-5297 I/O chip decodes full address range */
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port &= 0xFF;
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/* internal YM2413 chip */
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if ((port == 0xF0) || (port == 0xF1))
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{
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fm_write(Z80.cycles, port, data);
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return;
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}
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/* Audio control register (315-5297 I/O chip specific) */
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if (port == 0xF2)
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{
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/* D1 D0
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-----
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0 0 : enable only PSG output (power-on default)
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0 1 : enable only FM output
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1 0 : disable both PSG & FM output
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1 1 : enable both PSG and FM output
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*/
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psg_config(Z80.cycles, config.psg_preamp, ((data + 1) & 0x02) ? 0x00 : 0xFF);
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fm_write(Z80.cycles, 0x02, data);
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io_reg[6] = data;
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return;
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}
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}
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else if (!(port & 4))
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{
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/* external FM board */
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fm_write(Z80.cycles, port, data);
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return;
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}
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}
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z80_unused_port_w(port & 0xFF, data);
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return;
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}
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}
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}
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unsigned char z80_ms_port_r(unsigned int port)
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{
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switch (port & 0xC1)
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{
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case 0x00:
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case 0x01:
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{
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return z80_unused_port_r(port & 0xFF);
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}
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case 0x40:
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{
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return ((vdp_hvc_r(Z80.cycles) >> 8) & 0xFF);
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}
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case 0x41:
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{
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return (vdp_hvc_r(Z80.cycles) & 0xFF);
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}
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case 0x80:
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{
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return vdp_z80_data_r();
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}
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case 0x81:
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{
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return vdp_z80_ctrl_r(Z80.cycles);
|
|
}
|
|
|
|
default:
|
|
{
|
|
if (region_code == REGION_JAPAN_NTSC)
|
|
{
|
|
/* 315-5297 I/O chip decodes full address range */
|
|
port &= 0xFF;
|
|
|
|
if (port == 0xF2)
|
|
{
|
|
/* D7-D5 : C-SYNC counter (not emulated)
|
|
D4-D2 : Always zero
|
|
D1 : Mute control bit 1
|
|
D0 : Mute control bit 0
|
|
*/
|
|
return io_reg[0x06] & 0x03;
|
|
}
|
|
|
|
if ((port == 0xC0) || (port == 0xC1) || (port == 0xDC) || (port == 0xDD))
|
|
{
|
|
/* read I/O ports if enabled */
|
|
if (!(io_reg[0x0E] & 0x04))
|
|
{
|
|
return io_z80_read(port & 1);
|
|
}
|
|
}
|
|
|
|
return z80_unused_port_r(port);
|
|
}
|
|
else
|
|
{
|
|
uint8 data = 0xFF;
|
|
|
|
/* read FM board if enabled */
|
|
if (!(port & 4) && (config.ym2413 & 1))
|
|
{
|
|
data = fm_read(Z80.cycles, port);
|
|
}
|
|
|
|
/* read I/O ports if enabled */
|
|
if (!(io_reg[0x0E] & 0x04))
|
|
{
|
|
data &= io_z80_read(port & 1);
|
|
}
|
|
|
|
return data;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* Mark III port handlers */
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
void z80_m3_port_w(unsigned int port, unsigned char data)
|
|
{
|
|
switch (port & 0xC1)
|
|
{
|
|
case 0x00:
|
|
case 0x01:
|
|
{
|
|
z80_unused_port_w(port & 0xFF, data);
|
|
return;
|
|
}
|
|
|
|
case 0x40:
|
|
case 0x41:
|
|
{
|
|
psg_write(Z80.cycles, data);
|
|
return;
|
|
}
|
|
|
|
case 0x80:
|
|
{
|
|
vdp_z80_data_w(data);
|
|
return;
|
|
}
|
|
|
|
case 0x81:
|
|
{
|
|
vdp_sms_ctrl_w(data);
|
|
return;
|
|
}
|
|
|
|
default:
|
|
{
|
|
/* write to FM sound unit (FM-70) if enabled */
|
|
if (!(port & 4) && (config.ym2413 & 1))
|
|
{
|
|
fm_write(Z80.cycles, port, data);
|
|
|
|
/* FM output control "register" */
|
|
if (port & 2)
|
|
{
|
|
/* PSG output is automatically disabled (resp. enabled) by FM sound unit hardware if FM output is enabled (resp. disabled) */
|
|
psg_config(Z80.cycles, config.psg_preamp, (data & 0x01) ? 0x00 : 0xff);
|
|
}
|
|
return;
|
|
}
|
|
|
|
z80_unused_port_w(port & 0xFF, data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned char z80_m3_port_r(unsigned int port)
|
|
{
|
|
switch (port & 0xC1)
|
|
{
|
|
case 0x00:
|
|
case 0x01:
|
|
{
|
|
return z80_unused_port_r(port & 0xFF);
|
|
}
|
|
|
|
case 0x40:
|
|
{
|
|
return ((vdp_hvc_r(Z80.cycles) >> 8) & 0xFF);
|
|
}
|
|
|
|
case 0x41:
|
|
{
|
|
return (vdp_hvc_r(Z80.cycles) & 0xFF);
|
|
}
|
|
|
|
case 0x80:
|
|
{
|
|
return vdp_z80_data_r();
|
|
}
|
|
|
|
case 0x81:
|
|
{
|
|
return vdp_z80_ctrl_r(Z80.cycles);
|
|
}
|
|
|
|
default:
|
|
{
|
|
/* read FM sound unit (FM-70) if enabled */
|
|
if (!(port & 4) && (config.ym2413 & 1))
|
|
{
|
|
/* I/O ports are automatically disabled by FM sound unit hardware */
|
|
return fm_read(Z80.cycles, port);
|
|
}
|
|
|
|
/* read I/O ports */
|
|
return io_z80_read(port & 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* SG-1000 port handlers */
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
void z80_sg_port_w(unsigned int port, unsigned char data)
|
|
{
|
|
switch(port & 0xC1)
|
|
{
|
|
case 0x40:
|
|
case 0x41:
|
|
{
|
|
psg_write(Z80.cycles, data);
|
|
|
|
/* Z80 !WAIT input is tied to SN76489AN chip READY pin (held low for 32 clocks after each write access) */
|
|
Z80.cycles += (32 * 15);
|
|
return;
|
|
}
|
|
|
|
case 0x80:
|
|
{
|
|
vdp_z80_data_w(data);
|
|
return;
|
|
}
|
|
|
|
case 0x81:
|
|
{
|
|
vdp_tms_ctrl_w(data);
|
|
return;
|
|
}
|
|
|
|
default:
|
|
{
|
|
z80_unused_port_w(port & 0xFF, data);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned char z80_sg_port_r(unsigned int port)
|
|
{
|
|
switch (port & 0xC1)
|
|
{
|
|
case 0x80:
|
|
{
|
|
return vdp_z80_data_r();
|
|
}
|
|
|
|
case 0x81:
|
|
{
|
|
return vdp_z80_ctrl_r(Z80.cycles);
|
|
}
|
|
|
|
case 0xC0:
|
|
case 0xC1:
|
|
{
|
|
return io_z80_read(port & 1);
|
|
}
|
|
|
|
default:
|
|
{
|
|
return z80_unused_port_r(port & 0xFF);
|
|
}
|
|
}
|
|
}
|