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93 lines
3.8 KiB
C
93 lines
3.8 KiB
C
/****************************************************************************
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* Genesis Plus 1.2a
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* Serial EEPROM support
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*
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* code by Eke-Eke, GC/Wii port
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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***************************************************************************/
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#ifndef _EEPROM_H_
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#define _EEPROM_H_
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typedef enum
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{
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STAND_BY = 0,
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WAIT_STOP,
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GET_SLAVE_ADR,
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GET_WORD_ADR_7BITS,
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GET_WORD_ADR_HIGH,
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GET_WORD_ADR_LOW,
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WRITE_DATA,
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READ_DATA,
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} T_EEPROM_STATE;
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/* this defines the type of EEPROM inside the game cartridge as Backup RAM
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*
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* Here are some notes from 8BitWizard (http://www.spritesmind.net/_GenDev/forum):
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*
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* Mode 1 (7-bit) - the chip takes a single byte with a 7-bit memory address and a R/W bit (24C01)
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* Mode 2 (8-bit) - the chip takes a 7-bit device address and R/W bit followed by an 8-bit memory address;
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* the device address may contain up to three more memory address bits (24C01 - 24C16).
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* You can also string eight 24C01, four 24C02, two 24C08, or various combinations, set their address config lines correctly,
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* and the result appears exactly the same as a 24C16
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* Mode 3 (16-bit) - the chip takes a 7-bit device address and R/W bit followed by a 16-bit memory address (24C32 and larger)
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*
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* Also, while most 24Cxx are addressed at 200000-2FFFFF, I have found two different ways of mapping the control lines.
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* EA uses SDA on D7 (read/write) and SCL on D6 (write only), and I have found boards using different mapping (I think Accolade)
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* which uses D1-read=SDA, D0-write=SDA, D1-write=SCL. Accolade also has a custom-chip mapper which may even use a third method.
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*/
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typedef struct
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{
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uint8 address_bits; /* number of bits needed to address memory: 7, 8 or 16 */
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uint16 size_mask; /* depends on the max size of the memory (in bytes) */
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uint16 pagewrite_mask; /* depends on the maximal number of bytes that can be written in a single write cycle */
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uint32 sda_in_adr; /* 68000 memory address mapped to SDA_IN */
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uint32 sda_out_adr; /* 68000 memory address mapped to SDA_OUT */
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uint32 scl_adr; /* 68000 memory address mapped to SCL */
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uint8 sda_in_bit; /* bit offset for SDA_IN */
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uint8 sda_out_bit; /* bit offset for SDA_OUT */
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uint8 scl_bit; /* bit offset for SCL */
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} T_EEPROM_TYPE;
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typedef struct
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{
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uint8 sda; /* current /SDA line state */
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uint8 scl; /* current /SCL line state */
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uint8 old_sda; /* previous /SDA line state */
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uint8 old_scl; /* previous /SCL line state */
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uint8 cycles; /* current operation cycle number (0-9) */
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uint8 rw; /* operation type (1:READ, 0:WRITE) */
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uint16 slave_mask; /* device address (shifted by the memory address width)*/
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uint16 word_address; /* memory address */
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T_EEPROM_STATE state; /* current operation state */
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T_EEPROM_TYPE type; /* EEPROM characteristics for this game */
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} T_EEPROM;
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/* global variables */
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extern T_EEPROM eeprom;
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/* Function prototypes */
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extern void eeprom_init();
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extern void eeprom_write(uint32 address, uint32 value, uint32 word_access);
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extern uint32 eeprom_read(uint32 address, uint32 word_access);
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#endif
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