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Genesis Plus GX 1.6.0 ---------------------- [Core/Sound] --------------- * added YM2413 emulation in Master System compatibility mode. * fixed SN76489 noise boost initialization. * minor YM2612 core optimizations. [Core/VDP] --------------- * added accurate emulation of SG-1000, Master System (315-5124, 315-5246) & Game Gear VDP. * added support for all TMS9918 rendering modes. * improved Mega Drive VDP timings accuracy in Master System Compatibility mode. * fixed color palette initialization. * fixed shifted sprites rendering in Mode 4. * modified pixel rendering support (pixel depth is now forced at compilation time). [Core/CPU] --------------- * optimized 68k core (rewrote 68k interrupt handling, removed multiple CPU types support & unused code) for 5~8% speed improvment [Core/IO] --------------- * added accurate emulation of Master System (315-5216, 315-5237, 315-5297) & Game Gear I/O controllers. * added Terebi Oekaki tablet emulation. * improved Mouse emulation (fixes mouse support in Cannon Fodder). * improved Justifier emulation (fixes gun support in Lethal Enforcers 2). * improved 6-Buttons control pad emulation (fixes Duke Nukem 3D) * modified lightgun emulation to use common key inputs for all devices. * 2-buttons controller is now picked by default for Master System games. [Core/MD] --------------- * added copy-protection hardware emulation for some new dumped games (Tiny Toon Adventures 3, Mighty Morphin Power Rangers & The Battle of Red Cliffs). * added Game Toshokan in EEPROM database (verified on real cartridge). * fixed Micro Machines 2 - Turbo Tournament EEPROM size (verified on real cartridge). * modified SRAM banswitch hardware emulation to be more compatible with some hacks. [Core/MS] --------------- * added Cyborg Z to Korean mapper database. [Core/GG] --------------- * added 93C46 EEPROM emulation (Majors Pro Baseball, World Series Baseball & World Series Baseball 95). [Core/General] --------------- * added support for .mdx ROM format. * added Game Gear & SG-1000 ROM support. * added accurate emulation of SG-1000, Master System (I, II) & Game Gear hardware models for 100% compatibility. * updated to new Genesis Plus license (see http://cgfm2.emuviews.com/) * removed DOS port * various code cleanup. [Gamecube/Wii] --------------- * IMPORTANT: cheats, screenshots & save files are now stored in console-specific directories (ex: /snaps/md, /cheats/ms, /saves/gg, ...) * added 8-bit Action Replay & Game Genie codes support (for Master System & Game Gear games). * improved audio/video synchronization for PAL games in 50Hz TV modes (now use VSYNC like NTSC games in 60hz modes). * improved gun cursor positioning accuracy. * improved horizontal scaling & screenshots rendering in H32 mode. * fixed a bug with ROM file extension handling that would affect cheats, snapshots, sram & savestate files. * removed ARAM/injected ROM support (unused). * removed WPAD_ and PAD_ update from VSYNC callback. * increased GCC inlining limits for some speed improvment. * compiled with devkitPPC r24 & libogc 1.8.7.
489 lines
14 KiB
C
489 lines
14 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Internal Hardware & Bus controllers
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*
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* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive hardware
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2011 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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*
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* - Redistributions may not be sold, nor may they be used in a commercial
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* product or activity.
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*
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* - Redistributions that are modified from the original source must include the
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* complete source code, including the source code for all components used by a
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* binary built from the modified sources. However, as a special exception, the
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* source code distributed need not include anything that is normally distributed
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* (in either source or binary form) with the major components (compiler, kernel,
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* and so on) of the operating system on which the executable runs, unless that
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* component itself accompanies the executable.
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*
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* - Redistributions must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#include "shared.h"
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uint8 tmss[4]; /* TMSS security register */
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uint8 bios_rom[0x800]; /* OS ROM */
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uint8 work_ram[0x10000]; /* 68K RAM */
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uint8 zram[0x2000]; /* Z80 RAM */
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uint32 zbank; /* Z80 bank window address */
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uint8 zstate; /* Z80 bus state (d0 = BUSACK, d1 = /RESET) */
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/* PICO data */
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uint8 pico_current;
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uint8 pico_page[7];
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void gen_init(void)
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{
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int i;
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/* initialize 68k */
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m68k_init();
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/* initialize Z80 */
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z80_init(0,z80_irq_callback);
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/* initialize default 68k memory map */
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/* $000000-$7FFFFF : cartridge area (md_cart.c) */
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/* $800000-$DFFFFF : illegal access by default */
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for (i=0x80; i<0xe0; i++)
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{
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m68k_memory_map[i].base = work_ram; /* for VDP DMA */
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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/* $E00000-$FFFFFF : Work RAM */
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for (i=0xe0; i<0x100; i++)
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{
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m68k_memory_map[i].base = work_ram;
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m68k_memory_map[i].read8 = NULL;
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m68k_memory_map[i].read16 = NULL;
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m68k_memory_map[i].write8 = NULL;
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m68k_memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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/* $A10000-$A1FFFF : I/O & Control registers */
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m68k_memory_map[0xa1].read8 = ctrl_io_read_byte;
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m68k_memory_map[0xa1].read16 = ctrl_io_read_word;
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m68k_memory_map[0xa1].write8 = ctrl_io_write_byte;
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m68k_memory_map[0xa1].write16 = ctrl_io_write_word;
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zbank_memory_map[0xa1].read = zbank_read_ctrl_io;
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zbank_memory_map[0xa1].write = zbank_write_ctrl_io;
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/* $C0xxxx, $C8xxxx, $D0xxxx, $D8xxxx : VDP ports */
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = vdp_read_byte;
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m68k_memory_map[i].read16 = vdp_read_word;
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m68k_memory_map[i].write8 = vdp_write_byte;
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m68k_memory_map[i].write16 = vdp_write_word;
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zbank_memory_map[i].read = zbank_read_vdp;
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zbank_memory_map[i].write = zbank_write_vdp;
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}
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/* 68k mode */
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if (system_hw == SYSTEM_MD)
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{
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/* initialize Z80 memory map */
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/* $0000-$3FFF is mapped to Z80 RAM (8K mirrored) */
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/* $4000-$FFFF is mapped to hardware but Z80.PC should never point there */
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for (i=0; i<64; i++)
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{
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z80_readmap[i] = &zram[(i & 7) << 10];
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}
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/* initialize Z80 memory handlers */
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z80_writemem = z80_memory_w;
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z80_readmem = z80_memory_r;
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/* initialize Z80 port handlers */
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z80_writeport = z80_unused_port_w;
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z80_readport = z80_unused_port_r;
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/* initialize MD cartridge hardware */
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md_cart_init();
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}
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/* PICO hardware */
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else if (system_hw == SYSTEM_PICO)
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{
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/* additional registers mapped to $800000-$80FFFF */
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m68k_memory_map[0x80].read8 = pico_read_byte;
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m68k_memory_map[0x80].read16 = pico_read_word;
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m68k_memory_map[0x80].write8 = m68k_unused_8_w;
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m68k_memory_map[0x80].write16 = m68k_unused_16_w;
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/* there is no I/O area (Notaz) */
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m68k_memory_map[0xa1].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa1].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa1].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa1].write16 = m68k_unused_16_w;
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/* page registers */
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pico_current = 0x00;
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pico_page[0] = 0x00;
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pico_page[1] = 0x01;
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pico_page[2] = 0x03;
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pico_page[3] = 0x07;
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pico_page[4] = 0x0F;
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pico_page[5] = 0x1F;
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pico_page[6] = 0x3F;
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/* initialize cartridge hardware */
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md_cart_init();
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}
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/* Z80 mode */
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else
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{
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/* initialize cartridge hardware (memory handlers are also initialized) */
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sms_cart_init();
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/* initialize Z80 ports handlers */
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switch (system_hw)
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{
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case SYSTEM_PBC:
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{
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z80_writeport = z80_md_port_w;
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z80_readport = z80_md_port_r;
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break;
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}
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case SYSTEM_GG:
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case SYSTEM_GGMS:
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{
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z80_writeport = z80_gg_port_w;
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z80_readport = z80_gg_port_r;
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break;
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}
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case SYSTEM_SMS:
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case SYSTEM_SMS2:
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{
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z80_writeport = z80_ms_port_w;
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z80_readport = z80_ms_port_r;
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break;
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}
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case SYSTEM_MARKIII:
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{
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z80_writeport = z80_m3_port_w;
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z80_readport = z80_m3_port_r;
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break;
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}
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case SYSTEM_SG:
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{
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z80_writeport = z80_sg_port_w;
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z80_readport = z80_sg_port_r;
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break;
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}
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}
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}
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}
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void gen_reset(int hard_reset)
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{
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/* System Reset */
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if (hard_reset)
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{
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/* clear RAM */
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memset (work_ram, 0x00, sizeof (work_ram));
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memset (zram, 0x00, sizeof (zram));
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}
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else
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{
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/* reset YM2612 (on hard reset, this is done by sound_reset) */
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fm_reset(0);
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}
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/* 68k & Z80 could restart anywhere in VDP frame (Bonkers, Eternal Champions, X-Men 2) */
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mcycles_68k = mcycles_z80 = (uint32)((MCYCLES_PER_LINE * lines_per_frame) * ((double)rand() / (double)RAND_MAX));
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if ((system_hw & SYSTEM_PBC) == SYSTEM_MD)
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{
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/* reset cartridge hardware */
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md_cart_reset(hard_reset);
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/* Z80 bus is released & Z80 is reseted */
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m68k_memory_map[0xa0].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa0].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa0].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa0].write16 = m68k_unused_16_w;
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zstate = 0;
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/* assume default bank is $000000-$007FFF */
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zbank = 0;
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/* TMSS & OS ROM support */
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if (config.tmss & 1)
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{
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/* on HW reset only */
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if (hard_reset)
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{
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/* clear TMSS register */
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memset(tmss, 0x00, sizeof(tmss));
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/* VDP access is locked by default */
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int i;
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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/* OS ROM is mapped at $000000-$0007FF */
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if (config.tmss & 2)
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{
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m68k_memory_map[0].base = bios_rom;
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}
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}
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}
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/* reset 68k */
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m68k_pulse_reset();
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}
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else
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{
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/* Z80 cycles should a multiple of 15 to avoid rounding errors */
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mcycles_z80 = (mcycles_z80 / 15) * 15;
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/* reset cartridge hardware */
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sms_cart_reset();
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/* Z80 is running */
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zstate = 1;
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/* 68k is halted (/VRES is forced low) */
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m68k_pulse_halt();
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}
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/* reset Z80 */
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z80_reset();
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}
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void gen_shutdown(void)
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{
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z80_exit();
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}
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/*-----------------------------------------------------------------------*/
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/* OS ROM / TMSS register control functions (Genesis mode) */
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/*-----------------------------------------------------------------------*/
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void gen_tmss_w(unsigned int offset, unsigned int data)
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{
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/* write TMSS regisiter */
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WRITE_WORD(tmss, offset, data);
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/* VDP requires "SEGA" value to be written in TMSS register */
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int i;
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if (strncmp((char *)tmss, "SEGA", 4) == 0)
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{
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = vdp_read_byte;
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m68k_memory_map[i].read16 = vdp_read_word;
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m68k_memory_map[i].write8 = vdp_write_byte;
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m68k_memory_map[i].write16 = vdp_write_word;
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zbank_memory_map[i].read = zbank_read_vdp;
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zbank_memory_map[i].write = zbank_write_vdp;
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}
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}
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else
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{
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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}
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}
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void gen_bankswitch_w(unsigned int data)
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{
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/* OS ROM has not been loaded yet */
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if (!(config.tmss & 2))
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{
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config.tmss |= 2;
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memcpy(bios_rom, cart.rom, 0x800);
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memset(cart.rom, 0xff, cart.romsize);
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}
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if (data & 1)
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{
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/* enable CART */
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m68k_memory_map[0].base = cart.base;
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}
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else
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{
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/* enable internal BIOS ROM */
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m68k_memory_map[0].base = bios_rom;
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}
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}
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unsigned int gen_bankswitch_r(void)
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{
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return (m68k_memory_map[0].base == cart.base);
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}
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/*-----------------------------------------------------------------------*/
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/* Z80 Bus controller chip functions (Genesis mode) */
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/* ----------------------------------------------------------------------*/
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void gen_zbusreq_w(unsigned int data, unsigned int cycles)
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{
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if (data) /* !ZBUSREQ asserted */
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{
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/* check if Z80 is going to be stopped */
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if (zstate == 1)
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{
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/* resynchronize with 68k */
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z80_run(cycles);
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/* enable 68k access to Z80 bus */
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m68k_memory_map[0xa0].read8 = z80_read_byte;
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m68k_memory_map[0xa0].read16 = z80_read_word;
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m68k_memory_map[0xa0].write8 = z80_write_byte;
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m68k_memory_map[0xa0].write16 = z80_write_word;
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}
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/* update Z80 bus status */
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zstate |= 2;
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}
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else /* !ZBUSREQ released */
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{
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/* check if Z80 is going to be restarted */
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if (zstate == 3)
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{
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/* resynchronize with 68k */
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mcycles_z80 = cycles;
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/* disable 68k access to Z80 bus */
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m68k_memory_map[0xa0].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa0].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa0].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa0].write16 = m68k_unused_16_w;
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}
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/* update Z80 bus status */
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zstate &= 1;
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}
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}
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void gen_zreset_w(unsigned int data, unsigned int cycles)
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{
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if (data) /* !ZRESET released */
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{
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/* check if Z80 is going to be restarted */
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if (zstate == 0)
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{
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/* resynchronize with 68k */
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mcycles_z80 = cycles;
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/* reset Z80 & YM2612 */
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z80_reset();
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fm_reset(cycles);
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}
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/* check if 68k access to Z80 bus is granted */
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else if (zstate == 2)
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{
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/* enable 68k access to Z80 bus */
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m68k_memory_map[0xa0].read8 = z80_read_byte;
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m68k_memory_map[0xa0].read16 = z80_read_word;
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m68k_memory_map[0xa0].write8 = z80_write_byte;
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m68k_memory_map[0xa0].write16 = z80_write_word;
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/* reset Z80 & YM2612 */
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z80_reset();
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fm_reset(cycles);
|
|
}
|
|
|
|
/* update Z80 bus status */
|
|
zstate |= 1;
|
|
}
|
|
else /* !ZRESET asserted */
|
|
{
|
|
/* check if Z80 is going to be stopped */
|
|
if (zstate == 1)
|
|
{
|
|
/* resynchronize with 68k */
|
|
z80_run(cycles);
|
|
}
|
|
|
|
/* check if 68k had access to Z80 bus */
|
|
else if (zstate == 3)
|
|
{
|
|
/* disable 68k access to Z80 bus */
|
|
m68k_memory_map[0xa0].read8 = m68k_read_bus_8;
|
|
m68k_memory_map[0xa0].read16 = m68k_read_bus_16;
|
|
m68k_memory_map[0xa0].write8 = m68k_unused_8_w;
|
|
m68k_memory_map[0xa0].write16 = m68k_unused_16_w;
|
|
}
|
|
|
|
/* stop YM2612 */
|
|
fm_reset(cycles);
|
|
|
|
/* update Z80 bus status */
|
|
zstate &= 2;
|
|
}
|
|
}
|
|
|
|
void gen_zbank_w (unsigned int data)
|
|
{
|
|
zbank = ((zbank >> 1) | ((data & 1) << 23)) & 0xFF8000;
|
|
}
|
|
|
|
|
|
/*-----------------------------------------------------------------------*/
|
|
/* Z80 interrupt callback */
|
|
/* ----------------------------------------------------------------------*/
|
|
|
|
int z80_irq_callback (int param)
|
|
{
|
|
return 0xFF;
|
|
}
|