mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-05 10:25:07 +01:00
0d58ff65e0
fixed video glitches in games that switch video horizontal width. fixed BIOS infinite loop on hard reset
993 lines
28 KiB
C
993 lines
28 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Video Display Processor (memory handlers)
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Eke-Eke (2007,2008,2009), additional code & fixes for the GCN/Wii port
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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****************************************************************************************/
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#include "shared.h"
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#include "hvc.h"
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/* Pack and unpack CRAM data */
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#define PACK_CRAM(d) ((((d)&0xE00)>>9)|(((d)&0x0E0)>>2)|(((d)&0x00E)<<5))
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#define UNPACK_CRAM(d) ((((d)&0x1C0)>>5)|((d)&0x038)<<2|(((d)&0x007)<<9))
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/* Mark a pattern as dirty */
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#define MARK_BG_DIRTY(addr) \
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{ \
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name = (addr >> 5) & 0x7FF; \
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if(bg_name_dirty[name] == 0) bg_name_list[bg_list_index++] = name; \
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bg_name_dirty[name] |= (1 << ((addr >> 2) & 0x07)); \
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}
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/* VDP context */
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uint8 sat[0x400]; /* Internal copy of sprite attribute table */
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uint8 vram[0x10000]; /* Video RAM (64Kx8) */
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uint8 cram[0x80]; /* On-chip color RAM (64x9) */
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uint8 vsram[0x80]; /* On-chip vertical scroll RAM (40x11) */
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uint8 reg[0x20]; /* Internal VDP registers (23x8) */
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uint16 addr; /* Address register */
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uint16 addr_latch; /* Latched A15, A14 of address */
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uint8 code; /* Code register */
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uint8 pending; /* Pending write flag */
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uint16 status; /* VDP status flags */
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uint8 dmafill; /* next VDP Write is DMA Fill */
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uint8 hint_pending; /* 0= Line interrupt is pending */
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uint8 vint_pending; /* 1= Frame interrupt is pending */
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uint8 irq_status; /* Interrupt lines updated */
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/* Global variables */
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uint16 ntab; /* Name table A base address */
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uint16 ntbb; /* Name table B base address */
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uint16 ntwb; /* Name table W base address */
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uint16 satb; /* Sprite attribute table base address */
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uint16 hscb; /* Horizontal scroll table base address */
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uint8 border; /* Border color index */
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uint8 bg_name_dirty[0x800]; /* 1= This pattern is dirty */
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uint16 bg_name_list[0x800]; /* List of modified pattern indices */
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uint16 bg_list_index; /* # of modified patterns in list */
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uint8 bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
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uint8 playfield_shift; /* Width of planes A, B (in bits) */
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uint8 playfield_col_mask; /* Vertical scroll mask */
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uint16 playfield_row_mask; /* Horizontal scroll mask */
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uint32 y_mask; /* Name table Y-index bits mask */
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uint16 hc_latch; /* latched HCounter (INT2) */
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uint16 v_counter; /* VDP scanline counter */
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uint32 dma_length; /* Current DMA remaining bytes */
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int32 fifo_write_cnt; /* VDP writes fifo count */
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uint32 fifo_lastwrite; /* last VDP write cycle */
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uint8 fifo_latency; /* VDP write cycles latency */
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uint8 odd_frame; /* 1: odd field, 0: even field */
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uint8 im2_flag; /* 1= Interlace mode 2 is being used */
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uint8 interlaced; /* 1: Interlaced mode 1 or 2 */
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uint8 vdp_pal; /* 1: PAL , 0: NTSC (default) */
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uint8 vdp_rate; /* PAL: 50hz, NTSC: 60hz */
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uint16 lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
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/* Tables that define the playfield layout */
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static const uint8 shift_table[] = { 6, 7, 0, 8 };
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static const uint8 col_mask_table[] = { 0x0F, 0x1F, 0x0F, 0x3F };
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static const uint16 row_mask_table[] = { 0x0FF, 0x1FF, 0x2FF, 0x3FF };
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static const uint32 y_mask_table[] = { 0x1FC0, 0x1F80, 0x1FC0, 0x1F00 };
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static uint16 sat_base_mask; /* Base bits of SAT */
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static uint16 sat_addr_mask; /* Index bits of SAT */
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static uint32 dma_endCycles; /* 68k cycles to DMA end */
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static uint8 dma_type; /* DMA mode */
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/* DMA Timings
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According to the manual, here's a table that describes the transfer
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rates of each of the three DMA types:
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DMA Mode Width Display Transfer Count
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-----------------------------------------------------
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68K > VDP 32-cell Active 16
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Blanking 167
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40-cell Active 18
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Blanking 205
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VRAM Fill 32-cell Active 15
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Blanking 166
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40-cell Active 17
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Blanking 204
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VRAM Copy 32-cell Active 8
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Blanking 83
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40-cell Active 9
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Blanking 102
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'Active' is the active display period, 'Blanking' is either the vertical
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blanking period or when the display is forcibly blanked via register #1.
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The above transfer counts are all in bytes, unless the destination is
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CRAM or VSRAM for a 68K > VDP transfer, in which case it is in words.
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*/
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static const uint32 dma_rates[16] = {
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8, 83, 9, 102, /* 68K to VRAM (1 word = 2 bytes) */
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16, 167, 18, 205, /* 68K to CRAM or VSRAM */
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15, 166, 17, 204, /* DMA fill */
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8, 83, 9, 102, /* DMA Copy */
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};
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/*--------------------------------------------------------------------------*/
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/* Functions prototype */
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/*--------------------------------------------------------------------------*/
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static inline void fifo_update();
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static inline void data_w(unsigned int data);
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static inline void reg_w(unsigned int r, unsigned int d);
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static inline void dma_copy(void);
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static inline void dma_vbus (void);
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static inline void dma_fill(unsigned int data);
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void vdp_init(void)
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{
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/* PAL/NTSC timings */
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vdp_rate = vdp_pal ? 50 : 60;
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lines_per_frame = vdp_pal ? 313 : 262;
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}
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void vdp_reset(void)
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{
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memset ((char *) sat, 0, sizeof (sat));
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memset ((char *) vram, 0, sizeof (vram));
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memset ((char *) cram, 0, sizeof (cram));
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memset ((char *) vsram, 0, sizeof (vsram));
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memset ((char *) reg, 0, sizeof (reg));
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addr = 0;
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addr_latch = 0;
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code = 0;
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pending = 0;
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status = 0x200; /* fifo empty */
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status |= vdp_pal; /* PAL/NTSC flag */
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ntab = 0;
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ntbb = 0;
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ntwb = 0;
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satb = 0;
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hscb = 0;
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sat_base_mask = 0xFE00;
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sat_addr_mask = 0x01FF;
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border = 0x00;
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memset ((char *) bg_name_dirty, 0, sizeof (bg_name_dirty));
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memset ((char *) bg_name_list, 0, sizeof (bg_name_list));
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bg_list_index = 0;
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memset ((char *) bg_pattern_cache, 0, sizeof (bg_pattern_cache));
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playfield_shift = 6;
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playfield_col_mask = 0x0F;
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playfield_row_mask = 0x0FF;
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y_mask = 0x1FC0;
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hint_pending = 0;
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vint_pending = 0;
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irq_status = 0;
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hc_latch = 0;
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v_counter = 0;
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dmafill = 0;
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dma_length = 0;
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dma_endCycles = 0;
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im2_flag = 0;
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interlaced = 0;
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odd_frame = 0;
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fifo_write_cnt = 0;
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/* reset HVC tables */
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vctab = (vdp_pal) ? vc_pal_224 : vc_ntsc_224;
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hctab = cycle2hc32;
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/* reset display area */
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bitmap.viewport.w = 256;
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bitmap.viewport.h = 224;
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bitmap.viewport.oh = 256;
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bitmap.viewport.ow = 224;
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/* reset border area */
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bitmap.viewport.x = (reg[12] & 1) ? 16 : 12;
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bitmap.viewport.y = config.overscan ? (vdp_pal ? 32 : 8) : 0;
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bitmap.viewport.changed = 1;
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/* initialize some registers (normally set by BIOS) */
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if (config.bios_enabled != 3)
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{
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reg_w(1 , 0x04); /* Mode 5 enabled */
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reg_w(10, 0xff); /* HINT disabled */
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reg_w(12, 0x81); /* H40 mode */
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reg_w(15, 0x02); /* auto increment */
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}
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/* default latency */
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fifo_latency = 27;
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}
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void vdp_shutdown(void)
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{}
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void vdp_restore(uint8 *vdp_regs)
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{
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int i;
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for (i=0;i<0x20;i++)
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{
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reg_w(i, vdp_regs[i]);
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}
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/* reinitialize HVC tables */
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vctab = (vdp_pal) ? ((reg[1] & 8) ? vc_pal_240 : vc_pal_224) : vc_ntsc_224;
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hctab = (reg[12] & 1) ? cycle2hc40 : cycle2hc32;
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/* reinitialize overscan area */
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bitmap.viewport.x = (reg[12] & 1) ? 16 : 12;
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bitmap.viewport.y = config.overscan ? (((reg[1] & 8) ? 0 : 8) + (vdp_pal ? 24 : 0)) : 0;
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bitmap.viewport.changed = 1;
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/* restore VDP timings */
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fifo_latency = (reg[12] & 1) ? 27 : 30;
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if ((code & 0x0F) == 0x01) fifo_latency = fifo_latency * 2;
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/* remake cache */
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for (i=0;i<0x800;i++)
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{
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bg_name_list[i]=i;
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bg_name_dirty[i]=0xFF;
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}
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bg_list_index=0x800;
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/* reinitialize palette */
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color_update(0x00, *(uint16 *)&cram[border << 1]);
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for(i = 1; i < 0x40; i += 1)
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{
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color_update(i, *(uint16 *)&cram[i << 1]);
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}
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}
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/*--------------------------------------------------------------------------*/
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/* DMA Timings update */
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/*--------------------------------------------------------------------------*/
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void vdp_update_dma()
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{
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int dma_cycles = 0;
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/* DMA timings table index */
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int index = (4 * dma_type) + ((reg[12] & 1)*2);
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if ((status&8) || !(reg[1] & 0x40)) index++;
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/* DMA transfer rate */
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int rate = dma_rates[index];
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/* 68k cycles left */
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int left_cycles = (line_m68k + m68cycles_per_line) - count_m68k;
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if (left_cycles < 0) left_cycles = 0;
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/* DMA bytes left */
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int dma_bytes = (left_cycles * rate) / m68cycles_per_line;
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/* determinate DMA length in CPU cycles */
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if (dma_length < dma_bytes)
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{
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/* DMA will be finished during this line */
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dma_cycles = (dma_length * m68cycles_per_line) / rate;
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dma_length = 0;
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}
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else
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{
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/* DMA can not be finished until next scanline */
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dma_cycles = left_cycles;
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dma_length -= dma_bytes;
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}
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/* update 68k cycles counter */
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if (dma_type < 2)
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{
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/* 68K COPY to V-RAM */
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/* 68K is frozen during DMA operation */
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count_m68k += dma_cycles;
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}
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else
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{
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/* VRAM Fill or VRAM Copy */
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/* set DMA end cyles count */
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dma_endCycles = count_m68k + dma_cycles;
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/* set DMA Busy flag */
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status |= 0x0002;
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}
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}
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/*--------------------------------------------------------------------------*/
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/* VDP Ports handler */
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/*--------------------------------------------------------------------------*/
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void vdp_ctrl_w(unsigned int data)
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{
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if (pending == 0)
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{
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if ((data & 0xC000) == 0x8000)
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{
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/* VDP register write */
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uint8 r = (data >> 8) & 0x1F;
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uint8 d = data & 0xFF;
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reg_w(r,d);
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}
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else pending = 1;
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addr = ((addr_latch & 0xC000) | (data & 0x3FFF));
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code = ((code & 0x3C) | ((data >> 14) & 0x03));
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}
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else
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{
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/* Clear pending flag */
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pending = 0;
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/* Update address and code registers */
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addr = ((addr & 0x3FFF) | ((data & 3) << 14));
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code = ((code & 0x03) | ((data >> 2) & 0x3C));
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/* Save address bits A15 and A14 */
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addr_latch = (addr & 0xC000);
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/* DMA operation */
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if ((code & 0x20) && (reg[1] & 0x10))
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{
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switch (reg[23] & 0xC0)
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{
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case 0x00: /* V bus to VDP DMA */
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case 0x40: /* V bus to VDP DMA */
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dma_vbus();
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break;
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case 0x80: /* VRAM fill */
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dmafill = 1;
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break;
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case 0xC0: /* VRAM copy */
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dma_copy();
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break;
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}
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}
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}
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/* FIFO emulation:
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---------------
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HDISP is 256*10/7 = approx. 366 cycles (same for both modes)
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this gives:
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H32: 16 accesses --> 366/16 = 23 cycles per access
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H40: 20 accesses --> 366/20 = 18 cycles per access
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VRAM access are byte wide --> VRAM writes takes 2x CPU cycles
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Memory access requires some additional cyles, the following values
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seems to work fine (see Chaos Engine/Soldier of Fortune)
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*/
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fifo_latency = (reg[12] & 1) ? 27 : 30;
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if ((code & 0x0F) == 0x01) fifo_latency = fifo_latency * 2;
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}
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/*
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* Return VDP status
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*
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* Bits are
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* 0 0:1 ntsc:pal
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* 1 DMA Busy
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* 2 During HBlank
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* 3 During VBlank
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* 4 Frame Interlace 0:even 1:odd
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* 5 Sprite collision
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* 6 Too many sprites per line
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* 7 v interrupt occurred
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* 8 Write FIFO full
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* 9 Write FIFO empty
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* 10 - 15 Next word on bus
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*/
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unsigned int vdp_ctrl_r(void)
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{
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/* update FIFO flags */
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fifo_update();
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if (fifo_write_cnt < 4)
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{
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status &= 0xFEFF;
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if (fifo_write_cnt == 0) status |= 0x200;
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}
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else status ^= 0x200;
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/* update DMA Busy flag */
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if ((status & 2) && !dma_length && (count_m68k >= dma_endCycles))
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{
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status &= 0xFFFD;
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}
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unsigned int temp = status;
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/* display OFF: VBLANK flag is set */
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if (!(reg[1] & 0x40)) temp |= 0x8;
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/* HBLANK flag (Sonic 3 and Sonic 2 "VS Modes", Lemmings 2) */
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if ((count_m68k <= (line_m68k + 84)) || (count_m68k > (line_m68k + m68cycles_per_line))) temp |= 0x4;
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/* clear pending flag */
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pending = 0;
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/* clear SPR/SCOL flags */
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status &= 0xFF9F;
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return (temp);
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}
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void vdp_data_w(unsigned int data)
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{
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/* Clear pending flag */
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pending = 0;
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if (dmafill)
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{
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dma_fill(data);
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return;
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}
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/* update VDP FIFO (during HDISPLAY only) */
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if (!(status&8) && (reg[1]&0x40))
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{
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fifo_update();
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if (fifo_write_cnt == 0)
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{
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/* reset cycle counter */
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fifo_lastwrite = count_m68k;
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/* FIFO is not empty anymore */
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status &= 0xFDFF;
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}
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/* increase write counter */
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fifo_write_cnt ++;
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/* is FIFO full ? */
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if (fifo_write_cnt >= 4)
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{
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status |= 0x100;
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/* VDP latency (Chaos Engine, Soldiers of Fortune, Double Clutch) */
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if (fifo_write_cnt > 4) count_m68k = fifo_lastwrite + fifo_latency;
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}
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}
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/* write data */
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data_w(data);
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}
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unsigned int vdp_data_r(void)
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{
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uint16 temp = 0;
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/* Clear pending flag */
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pending = 0;
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switch (code & 0x0F)
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{
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case 0x00: /* VRAM */
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temp = *(uint16 *) & vram[(addr & 0xFFFE)];
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break;
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case 0x08: /* CRAM */
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temp = *(uint16 *) & cram[(addr & 0x7E)];
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temp = UNPACK_CRAM (temp);
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break;
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case 0x04: /* VSRAM */
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temp = *(uint16 *) & vsram[(addr & 0x7E)];
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break;
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}
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/* Increment address register */
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addr += reg[15];
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/* return data */
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return (temp);
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}
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unsigned int vdp_hvc_r(void)
|
|
{
|
|
uint8 hc = (hc_latch & 0x100) ? (hc_latch & 0xFF) : hctab[count_m68k % m68cycles_per_line];
|
|
uint8 vc = vctab[v_counter];
|
|
|
|
/* interlace mode 2 */
|
|
if (im2_flag) vc = (vc << 1) | ((vc >> 7) & 1);
|
|
|
|
return ((vc << 8) | hc);
|
|
}
|
|
|
|
void vdp_test_w(unsigned int value)
|
|
{
|
|
#ifdef LOGERROR
|
|
error("Unused VDP Write 0x%x (%08x)\n", value, m68k_get_reg (NULL, M68K_REG_PC));
|
|
#endif
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* VDP Interrupts callback */
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
int vdp_int_ack_callback(int int_level)
|
|
{
|
|
/* VINT triggered ? */
|
|
if (irq_status&0x20)
|
|
{
|
|
vint_pending = 0;
|
|
status &= ~0x80; /* clear VINT flag */
|
|
}
|
|
else
|
|
{
|
|
hint_pending = 0;
|
|
}
|
|
|
|
/* update IRQ status */
|
|
irq_status = 0x10;
|
|
if (vint_pending && (reg[1] & 0x20)) irq_status |= 6;
|
|
else if (hint_pending && (reg[0] & 0x10)) irq_status |= 4;
|
|
|
|
return M68K_INT_ACK_AUTOVECTOR;
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* FIFO emulation */
|
|
/*--------------------------------------------------------------------------*/
|
|
static inline void fifo_update()
|
|
{
|
|
if (fifo_write_cnt > 0)
|
|
{
|
|
/* update FIFO reads */
|
|
uint32 fifo_read = ((count_m68k - fifo_lastwrite) / fifo_latency);
|
|
if (fifo_read > 0)
|
|
{
|
|
fifo_write_cnt -= fifo_read;
|
|
if (fifo_write_cnt < 0) fifo_write_cnt = 0;
|
|
|
|
/* update cycle count */
|
|
fifo_lastwrite += fifo_read*fifo_latency;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* Memory access functions */
|
|
/*--------------------------------------------------------------------------*/
|
|
static inline void data_w(unsigned int data)
|
|
{
|
|
switch (code & 0x0F)
|
|
{
|
|
case 0x01: /* VRAM */
|
|
|
|
/* Byte-swap data if A0 is set */
|
|
if (addr & 1) data = (data >> 8) | (data << 8);
|
|
|
|
/* Copy SAT data to the internal SAT */
|
|
if ((addr & sat_base_mask) == satb)
|
|
{
|
|
*(uint16 *) &sat[addr & sat_addr_mask & 0xFFFE] = data;
|
|
}
|
|
|
|
/* Only write unique data to VRAM */
|
|
if (data != *(uint16 *) &vram[addr & 0xFFFE])
|
|
{
|
|
/* Write data to VRAM */
|
|
*(uint16 *) &vram[addr & 0xFFFE] = data;
|
|
|
|
/* Update the pattern cache */
|
|
int name;
|
|
MARK_BG_DIRTY (addr);
|
|
}
|
|
break;
|
|
|
|
case 0x03: /* CRAM */
|
|
{
|
|
uint16 *p = (uint16 *) &cram[(addr & 0x7E)];
|
|
data = PACK_CRAM (data & 0x0EEE);
|
|
if (data != *p)
|
|
{
|
|
int index = (addr >> 1) & 0x3F;
|
|
*p = data;
|
|
if (index) color_update (index, *p);
|
|
if (border == index) color_update (0x00, *p);
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0x05: /* VSRAM */
|
|
*(uint16 *) &vsram[(addr & 0x7E)] = data;
|
|
break;
|
|
}
|
|
|
|
/* Increment address register */
|
|
addr += reg[15];
|
|
}
|
|
|
|
/*
|
|
The reg[] array is updated at the *end* of this function, so the new
|
|
register data can be compared with the previous data.
|
|
*/
|
|
static inline void reg_w(unsigned int r, unsigned int d)
|
|
{
|
|
/* See if Mode 4 (SMS mode) is enabled
|
|
According to official doc, VDP registers #11 to #23 can not be written unless bit2 in register #1 is set
|
|
Fix Captain Planet & Avengers (Alt version), Bass Master Classic Pro Edition (they incidentally activate Mode 4)
|
|
*/
|
|
if (!(reg[1] & 4) && (r > 10)) return;
|
|
|
|
switch(r)
|
|
{
|
|
case 0: /* CTRL #1 */
|
|
|
|
/* Line Interrupt */
|
|
if (((d&0x10) != (reg[0]&0x10)) && hint_pending)
|
|
{
|
|
/* update IRQ status */
|
|
irq_status = 0x50;
|
|
if (vint_pending && (reg[1] & 0x20)) irq_status |= 0x26;
|
|
else if (d & 0x10) irq_status |= 4;
|
|
}
|
|
|
|
/* Palette bit */
|
|
if ((d&0x04) != (reg[0]&0x04))
|
|
{
|
|
/* Update colors */
|
|
reg[0] = d;
|
|
int i;
|
|
color_update (0x00, *(uint16 *) & cram[border << 1]);
|
|
for (i = 1; i < 0x40; i += 1)
|
|
{
|
|
color_update (i, *(uint16 *) & cram[i << 1]);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 1: /* CTRL #2 */
|
|
|
|
/* Frame Interrupt */
|
|
if (((d&0x20) != (reg[1]&0x20)) && vint_pending)
|
|
{
|
|
/* update IRQ status */
|
|
irq_status = 0x50;
|
|
if (d & 0x20) irq_status |= 0x26;
|
|
else if (hint_pending && (reg[0] & 0x10)) irq_status |= 4;
|
|
}
|
|
|
|
/* See if the viewport height has actually been changed */
|
|
if ((d & 8) != (reg[1] & 8))
|
|
{
|
|
/* update viewport */
|
|
bitmap.viewport.changed = 1;
|
|
bitmap.viewport.h = (d & 8) ? 240 : 224;
|
|
if (config.overscan)
|
|
{
|
|
bitmap.viewport.y = ((vdp_pal ? 288 : 240) - bitmap.viewport.h) / 2;
|
|
}
|
|
|
|
/* update VC table */
|
|
if (vdp_pal) vctab = (d & 8) ? vc_pal_240 : vc_pal_224;
|
|
}
|
|
|
|
/* Display activated/blanked during Horizontal Blanking */
|
|
if (((d&0x40) != (reg[1]&0x40)) && !(status & 8))
|
|
{
|
|
if (count_m68k <= (hint_m68k + 120))
|
|
{
|
|
/* Redraw the current line :
|
|
- Legend of Galahad, Lemmings 2, Nigel Mansell's World Championship Racing (set display OFF)
|
|
- Deadly Moves aka Power Athlete (set display ON)
|
|
*/
|
|
reg[1] = d;
|
|
render_line(v_counter, 0);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 2: /* NTAB */
|
|
ntab = (d << 10) & 0xE000;
|
|
break;
|
|
|
|
case 3: /* NTWB */
|
|
ntwb = (d << 10) & 0xF800;
|
|
if(reg[12] & 1) ntwb &= 0xF000;
|
|
break;
|
|
|
|
case 4: /* NTBB */
|
|
ntbb = (d << 13) & 0xE000;
|
|
break;
|
|
|
|
case 5: /* SATB */
|
|
if (reg[12] & 1)
|
|
{
|
|
sat_base_mask = 0xFC00;
|
|
sat_addr_mask = 0x03FF;
|
|
}
|
|
else
|
|
{
|
|
sat_base_mask = 0xFE00;
|
|
sat_addr_mask = 0x01FF;
|
|
}
|
|
satb = (d << 9) & sat_base_mask;
|
|
break;
|
|
|
|
case 7:
|
|
/* See if the border color has actually changed */
|
|
d &= 0x3F;
|
|
if (d != border)
|
|
{
|
|
/* Mark the border color as modified */
|
|
border = d;
|
|
color_update(0x00, *(uint16 *)&cram[(border << 1)]);
|
|
|
|
/* background color modified during Horizontal Blanking */
|
|
if (!(status & 8) && (count_m68k <= (line_m68k + 84)))
|
|
{
|
|
/* remap current line (see Road Rash I,II,III) */
|
|
reg[7] = d;
|
|
remap_buffer(v_counter,bitmap.viewport.w + 2*bitmap.viewport.x);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 12:
|
|
/* See if the viewport width has actually been changed */
|
|
if ((d & 1) != (reg[12] & 1))
|
|
{
|
|
if (d & 1)
|
|
{
|
|
/* Update display-dependant registers */
|
|
ntwb = (reg[3] << 10) & 0xF000;
|
|
sat_base_mask = 0xFC00;
|
|
sat_addr_mask = 0x03FF;
|
|
satb = (reg[5] << 9) & sat_base_mask;
|
|
|
|
/* Update HC table */
|
|
hctab = cycle2hc40;
|
|
|
|
/* Update viewport width */
|
|
bitmap.viewport.w = 320;
|
|
if (config.overscan) bitmap.viewport.x = 16;
|
|
}
|
|
else
|
|
{
|
|
/* Update display-dependant registers */
|
|
ntwb = (reg[3] << 10) & 0xF800;
|
|
sat_base_mask = 0xFE00;
|
|
sat_addr_mask = 0x01FF;
|
|
satb = (reg[5] << 9) & sat_base_mask;
|
|
|
|
/* Update HC table */
|
|
hctab = cycle2hc32;
|
|
|
|
/* Update viewport width */
|
|
bitmap.viewport.w = 256;
|
|
if (config.overscan) bitmap.viewport.x = 12;
|
|
}
|
|
|
|
/* Update viewport */
|
|
bitmap.viewport.changed = 1;
|
|
|
|
/* Update clipping */
|
|
window_clip();
|
|
}
|
|
|
|
/* See if the S/TE mode bit has changed */
|
|
if ((d & 8) != (reg[12] & 8))
|
|
{
|
|
int i;
|
|
|
|
/* The following color update check this value */
|
|
reg[12] = d;
|
|
|
|
/* Update colors */
|
|
color_update (0x00, *(uint16 *) & cram[border << 1]);
|
|
for (i = 1; i < 0x40; i += 1)
|
|
{
|
|
color_update (i, *(uint16 *) & cram[i << 1]);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 13: /* HSCB */
|
|
hscb = (d << 10) & 0xFC00;
|
|
break;
|
|
|
|
case 16: /* Playfield size */
|
|
playfield_shift = shift_table[(d & 3)];
|
|
playfield_col_mask = col_mask_table[(d & 3)];
|
|
playfield_row_mask = row_mask_table[(d >> 4) & 3];
|
|
y_mask = y_mask_table[(d & 3)];
|
|
break;
|
|
|
|
case 17: /* Update clipping */
|
|
reg[17] = d;
|
|
window_clip();
|
|
break;
|
|
}
|
|
|
|
/* Write new register value */
|
|
reg[r] = d;
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
/* DMA Operations */
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/* DMA Copy
|
|
Read byte from VRAM (source), write to VRAM (addr),
|
|
bump source and add r15 to addr.
|
|
|
|
- see how source addr is affected
|
|
(can it make high source byte inc?)
|
|
*/
|
|
static inline void dma_copy(void)
|
|
{
|
|
int name;
|
|
int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
|
|
int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
|
|
if (!length) length = 0x10000;
|
|
|
|
dma_type = 3;
|
|
dma_length = length;
|
|
vdp_update_dma();
|
|
|
|
/* proceed DMA */
|
|
do
|
|
{
|
|
vram[addr] = vram[source];
|
|
MARK_BG_DIRTY(addr);
|
|
source = (source + 1) & 0xFFFF;
|
|
addr += reg[15];
|
|
} while (--length);
|
|
|
|
/* update length & source address registers */
|
|
reg[19] = length & 0xFF;
|
|
reg[20] = (length >> 8) & 0xFF;
|
|
reg[21] = source & 0xFF; /* not sure */
|
|
reg[22] = (source >> 8) & 0xFF;
|
|
}
|
|
|
|
/* 68K Copy to VRAM, VSRAM or CRAM */
|
|
static inline void dma_vbus (void)
|
|
{
|
|
uint32 base, source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
|
|
uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
|
|
uint32 temp;
|
|
|
|
if (!length) length = 0x10000;
|
|
base = source;
|
|
|
|
/* DMA timings */
|
|
dma_type = (code & 0x06) ? 1 : 0;
|
|
dma_length = length;
|
|
vdp_update_dma();
|
|
|
|
/* DMA source */
|
|
if ((source >> 17) == 0x50)
|
|
{
|
|
/* Z80 & I/O area */
|
|
do
|
|
{
|
|
/* Return $FFFF only when the Z80 isn't hogging the Z-bus.
|
|
(e.g. Z80 isn't reset and 68000 has the bus) */
|
|
if (source <= 0xa0ffff) temp = (zbusack ? *(uint16 *)(work_ram + (source & 0xffff)) : 0xffff);
|
|
|
|
/* The I/O chip and work RAM try to drive the data bus which results
|
|
in both values being combined in random ways when read.
|
|
We return the I/O chip values which seem to have precedence, */
|
|
else if (source <= 0xa1001f)
|
|
{
|
|
temp = io_read((source >> 1) & 0x0f);
|
|
temp = (temp << 8 | temp);
|
|
}
|
|
|
|
/* All remaining locations access work RAM */
|
|
else temp = *(uint16 *)(work_ram + (source & 0xffff));
|
|
|
|
source += 2;
|
|
source = ((base & 0xFE0000) | (source & 0x1FFFF));
|
|
data_w(temp);
|
|
}
|
|
while (--length);
|
|
}
|
|
else
|
|
{
|
|
/* SVP latency */
|
|
if (svp && (source < 0x400000))
|
|
{
|
|
source = (source - 2);
|
|
}
|
|
|
|
/* ROM & RAM */
|
|
do
|
|
{
|
|
temp = *(uint16 *)(m68k_memory_map[source>>16].base + (source & 0xffff));
|
|
source += 2;
|
|
source = ((base & 0xFE0000) | (source & 0x1FFFF));
|
|
data_w(temp);
|
|
}
|
|
while (--length);
|
|
}
|
|
|
|
/* update length & source address registers */
|
|
reg[19] = length & 0xFF;
|
|
reg[20] = (length >> 8) & 0xFF;
|
|
reg[21] = (source >> 1) & 0xFF;
|
|
reg[22] = (source >> 9) & 0xFF;
|
|
reg[23] = (reg[23] & 0x80) | ((source >> 17) & 0x7F);
|
|
}
|
|
|
|
/* VRAM FILL */
|
|
static inline void dma_fill(unsigned int data)
|
|
{
|
|
int name;
|
|
int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
|
|
if (!length) length = 0x10000;
|
|
|
|
/* DMA timings */
|
|
dma_type = 2;
|
|
dma_length = length;
|
|
vdp_update_dma();
|
|
|
|
/* proceed DMA */
|
|
data_w(data);
|
|
|
|
/* write MSB */
|
|
data = (data >> 8) & 0xff;
|
|
|
|
/* detect internal SAT modification */
|
|
if ((addr & sat_base_mask) == satb)
|
|
{
|
|
do
|
|
{
|
|
/* update internal SAT (fix Battletech) */
|
|
WRITE_BYTE(sat, (addr & sat_addr_mask)^1, data);
|
|
WRITE_BYTE(vram, addr^1, data);
|
|
MARK_BG_DIRTY (addr);
|
|
addr += reg[15];
|
|
}
|
|
while (--length);
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
WRITE_BYTE(vram, addr^1, data);
|
|
MARK_BG_DIRTY (addr);
|
|
addr += reg[15];
|
|
}
|
|
while (--length);
|
|
}
|
|
|
|
/* update length register */
|
|
reg[19] = length & 0xFF;
|
|
reg[20] = (length >> 8) & 0xFF;
|
|
dmafill = 0;
|
|
}
|