mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-05 10:25:07 +01:00
28775cc3aa
---------- * added Mega CD / Sega CD hardware emulation (incl. Sub 68K, CDD, CDC, PCM, GFX rotation/scaling, etc) * added .ISO & .BIN CD image file support * added 512K backup cartridge RAM support * added savestate support for CD games NOTES: ~~~~~~ * to play CD games, original BIOS ROM files are required in /genplus/bios/ directory: unzip & rename them to bios_CD_U.bin, bios_CD_E.bin, bios_CD_J.bin * CD audio tracks (CD-DA) are not supported (yet) [Core/CPU] ---------- * modified 68k core for Mega CD / Sega CD support [Core/VDP] --------------- * improved DMA accuracy * added support for 8-bit VRAM writes with undocumented code value (verified on real hardware by Nemesis) [Gamecube/Wii] --------------- * modified Master System & Game Gear "BIOS" support (files should be named bios_U.sms, bios_J.sms, bios_E.sms & bios.gg and copied to /genplus/bios directory). * replaced "Hard Reset" button by a Soft Reset for systems having a Reset button (Mega Drive / Genesis & Master System) * State & SRAM files are now only compressed when saving to Gamecube Memory Cards * various fixes & cleanup. [Core/SCD] ---------- * added Mega CD / Sega CD hardware emulation (incl. Sub 68K, CDD, CDC, PCM, GFX rotation/scaling, etc) * added .ISO & .BIN CD image file support * added 512K backup cartridge RAM support * added savestate support for CD games NOTES: ~~~~~~ * to play CD games, original BIOS ROM files are required in /genplus/bios/ directory: unzip & rename them to bios_CD_U.bin, bios_CD_E.bin, bios_CD_J.bin * CD audio tracks (CD-DA) are not supported (yet) [Core/CPU] ---------- * modified 68k core for Mega CD / Sega CD support [Core/VDP] --------------- * improved DMA accuracy * added support for 8-bit VRAM writes with undocumented code value (verified on real hardware by Nemesis) [Gamecube/Wii] --------------- * modified Master System & Game Gear "BIOS" support (files should be named bios_U.sms, bios_J.sms, bios_E.sms & bios.gg and copied to /genplus/bios directory). * replaced "Hard Reset" button by a Soft Reset for systems having a Reset button (Mega Drive / Genesis & Master System) * State & SRAM files are now only compressed when saving to Gamecube Memory Cards * various fixes & cleanup.
627 lines
16 KiB
C
627 lines
16 KiB
C
/***************************************************************************************
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* Genesis Plus
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* CD data controller (LC89510 compatible)
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*
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* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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*
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* - Redistributions may not be sold, nor may they be used in a commercial
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* product or activity.
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*
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* - Redistributions that are modified from the original source must include the
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* complete source code, including the source code for all components used by a
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* binary built from the modified sources. However, as a special exception, the
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* source code distributed need not include anything that is normally distributed
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* (in either source or binary form) with the major components (compiler, kernel,
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* and so on) of the operating system on which the executable runs, unless that
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* component itself accompanies the executable.
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*
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* - Redistributions must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#include "shared.h"
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/* IFSTAT register bitmasks */
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#define BIT_DTEI 0x40
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#define BIT_DECI 0x20
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#define BIT_DTBSY 0x08
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#define BIT_DTEN 0x02
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/* IFCTRL register bitmasks */
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#define BIT_DTEIEN 0x40
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#define BIT_DECIEN 0x20
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#define BIT_DOUTEN 0x02
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/* CTRL0 register bitmasks */
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#define BIT_DECEN 0x80
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#define BIT_E01RQ 0x20
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#define BIT_AUTORQ 0x10
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#define BIT_WRRQ 0x04
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/* CTRL1 register bitmasks */
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#define BIT_MODRQ 0x08
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#define BIT_FORMRQ 0x04
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#define BIT_SHDREN 0x01
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/* CTRL2 register bitmask */
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#define BIT_VALST 0x80
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/* TODO: figure exact DMA transfer rate */
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#define DMA_BYTES_PER_LINE 512
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void cdc_init(void)
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{
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memset(&cdc, 0, sizeof(cdc_t));
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}
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void cdc_reset(void)
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{
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/* reset CDC register index */
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scd.regs[0x04>>1].byte.l = 0x00;
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/* reset CDC registers */
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cdc.ifstat = 0xff;
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cdc.ifctrl = 0x00;
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cdc.ctrl[0] = 0x00;
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cdc.ctrl[1] = 0x00;
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cdc.stat[0] = 0x00;
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cdc.stat[1] = 0x00;
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cdc.stat[2] = 0x00;
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cdc.stat[3] = 0x80;
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cdc.head[0][0] = 0x00;
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cdc.head[0][1] = 0x00;
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cdc.head[0][2] = 0x00;
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cdc.head[0][3] = 0x01;
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cdc.head[1][0] = 0x00;
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cdc.head[1][1] = 0x00;
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cdc.head[1][2] = 0x00;
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cdc.head[1][3] = 0x00;
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/* reset CDC cycle counter */
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cdc.cycles = 0;
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/* DMA transfer disabled */
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cdc.dma_w = 0;
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/* clear any pending IRQ */
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if (scd.pending & (1 << 5))
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{
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/* clear any pending interrupt level 5 */
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scd.pending &= ~(1 << 5);
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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}
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void cdc_dma_update(void)
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{
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/* maximal transfer length */
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int length = DMA_BYTES_PER_LINE;
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/* end of DMA transfer ? */
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if (cdc.dbc.w < DMA_BYTES_PER_LINE)
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{
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/* transfer remaining words using 16-bit DMA */
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cdc.dma_w((cdc.dbc.w + 1) >> 1);
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/* reset data byte counter (DBCH bits 4-7 should be set to 1) */
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cdc.dbc.w = 0xf000;
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/* clear !DTEN and !DTBSY */
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cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
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/* pending Data Transfer End interrupt */
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cdc.ifstat &= ~BIT_DTEI;
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/* Data Transfer End interrupt enabled ? */
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if (cdc.ifctrl & BIT_DTEIEN)
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{
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/* pending level 5 interrupt */
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scd.pending |= (1 << 5);
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/* level 5 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x20)
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{
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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}
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/* clear DSR bit & set EDT bit (SCD register $04) */
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scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
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/* disable DMA transfer */
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cdc.dma_w = 0;
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}
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else
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{
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/* transfer all words using 16-bit DMA */
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cdc.dma_w(DMA_BYTES_PER_LINE >> 1);
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/* decrement data byte counter */
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cdc.dbc.w -= length;
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}
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}
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int cdc_decoder_update(uint32 header)
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{
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/* data decoding enabled ? */
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if (cdc.ctrl[0] & BIT_DECEN)
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{
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/* update HEAD registers */
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*(uint32 *)(cdc.head[0]) = header;
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/* set !VALST */
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cdc.stat[3] = 0x00;
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/* pending decoder interrupt */
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cdc.ifstat &= ~BIT_DECI;
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/* decoder interrupt enabled ? */
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if (cdc.ifctrl & BIT_DECIEN)
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{
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/* pending level 5 interrupt */
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scd.pending |= (1 << 5);
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/* level 5 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x20)
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{
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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}
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/* buffer RAM write enabled ? */
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if (cdc.ctrl[0] & BIT_WRRQ)
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{
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uint16 offset;
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/* increment block pointer */
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cdc.pt.w += 2352;
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/* increment write address */
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cdc.wa.w += 2352;
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/* CDC buffer address */
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offset = cdc.pt.w & 0x3fff;
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/* write CDD block header (4 bytes) */
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*(uint32 *)(cdc.ram + offset) = header;
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/* write CDD block data (2048 bytes) */
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cdd_read(cdc.ram + 4 + offset);
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/* take care of buffer overrun */
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if (offset > (0x4000 - 2048 - 4))
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{
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/* data should be written at the start of buffer */
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memcpy(cdc.ram, cdc.ram + 0x4000, offset + 2048 + 4 - 0x4000);
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}
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/* read next data block */
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return 1;
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}
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}
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/* keep decoding same data block if Buffer Write is disabled */
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return 0;
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}
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void cdc_reg_w(unsigned char data)
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{
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#ifdef LOG_CDC
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error("CDC register %X write 0x%04x (%X)\n", scd.regs[0x04>>1].byte.l & 0x0F, data, s68k.pc);
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#endif
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switch (scd.regs[0x04>>1].byte.l & 0x0F)
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{
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case 0x01: /* IFCTRL */
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{
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/* pending interrupts ? */
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if (((data & BIT_DTEIEN) && !(cdc.ifstat & BIT_DTEI)) ||
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((data & BIT_DECIEN) && !(cdc.ifstat & BIT_DECI)))
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{
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/* pending level 5 interrupt */
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scd.pending |= (1 << 5);
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/* level 5 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x20)
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{
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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}
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else if (scd.pending & (1 << 5))
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{
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/* clear pending level 5 interrupts */
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scd.pending &= ~(1 << 5);
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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/* abort any data transfer if data output is disabled */
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if (!(data & BIT_DOUTEN))
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{
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/* clear !DTBSY and !DTEN */
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cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
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}
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cdc.ifctrl = data;
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scd.regs[0x04>>1].byte.l = 0x02;
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break;
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}
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case 0x02: /* DBCL */
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cdc.dbc.byte.l = data;
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scd.regs[0x04>>1].byte.l = 0x03;
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break;
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case 0x03: /* DBCH */
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cdc.dbc.byte.h = data;
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scd.regs[0x04>>1].byte.l = 0x04;
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break;
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case 0x04: /* DACL */
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cdc.dac.byte.l = data;
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scd.regs[0x04>>1].byte.l = 0x05;
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break;
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case 0x05: /* DACH */
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cdc.dac.byte.h = data;
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scd.regs[0x04>>1].byte.l = 0x06;
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break;
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case 0x06: /* DTRG */
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{
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/* start data transfer if data output is enabled */
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if (cdc.ifctrl & BIT_DOUTEN)
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{
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/* set !DTBSY */
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cdc.ifstat &= ~BIT_DTBSY;
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/* clear DBCH bits 4-7 */
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cdc.dbc.byte.h &= 0x0f;
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/* clear EDT & DSR bits (SCD register $04) */
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scd.regs[0x04>>1].byte.h &= 0x07;
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/* setup data transfer destination */
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switch (scd.regs[0x04>>1].byte.h & 0x07)
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{
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case 2: /* MAIN-CPU host read */
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case 3: /* SUB-CPU host read */
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{
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/* set !DTEN */
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cdc.ifstat &= ~BIT_DTEN;
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/* set DSR bit (register $04) */
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scd.regs[0x04>>1].byte.h |= 0x40;
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break;
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}
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case 4: /* PCM RAM DMA */
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{
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cdc.dma_w = pcm_ram_dma_w;
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break;
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}
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case 5: /* PRG-RAM DMA */
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{
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cdc.dma_w = prg_ram_dma_w;
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break;
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}
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case 7: /* WORD-RAM DMA */
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{
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/* check memory mode */
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if (scd.regs[0x02 >> 1].byte.l & 0x04)
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{
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/* 1M mode */
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if (scd.regs[0x02 >> 1].byte.l & 0x01)
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{
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/* Word-RAM bank 0 is assigned to SUB-CPU */
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cdc.dma_w = word_ram_0_dma_w;
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}
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else
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{
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/* Word-RAM bank 1 is assigned to SUB-CPU */
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cdc.dma_w = word_ram_1_dma_w;
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}
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}
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else
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{
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/* 2M mode */
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if (scd.regs[0x02 >> 1].byte.l & 0x02)
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{
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/* only process DMA if Word-RAM is assigned to SUB-CPU */
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cdc.dma_w = word_ram_2M_dma_w;
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}
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}
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break;
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}
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default: /* invalid */
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{
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#ifdef LOG_CDC
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error("invalid CDC tranfer destination (%d)\n", scd.regs[0x04>>1].byte.h & 0x07);
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#endif
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break;
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}
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}
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}
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scd.regs[0x04>>1].byte.l = 0x07;
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break;
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}
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case 0x07: /* DTACK */
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{
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/* clear pending data transfer end interrupt */
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cdc.ifstat |= BIT_DTEI;
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/* clear DBCH bits 4-7 */
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cdc.dbc.byte.h &= 0x0f;
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#if 0
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/* no pending decoder interrupt ? */
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if ((cdc.ifstat | BIT_DECI) || !(cdc.ifctrl & BIT_DECIEN))
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{
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/* clear pending level 5 interrupt */
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scd.pending &= ~(1 << 5);
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/* update IRQ level */
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s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
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}
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#endif
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scd.regs[0x04>>1].byte.l = 0x08;
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break;
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}
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case 0x08: /* WAL */
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cdc.wa.byte.l = data;
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scd.regs[0x04>>1].byte.l = 0x09;
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break;
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case 0x09: /* WAH */
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cdc.wa.byte.h = data;
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scd.regs[0x04>>1].byte.l = 0x0a;
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break;
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case 0x0a: /* CTRL0 */
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{
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/* set CRCOK bit only if decoding is enabled */
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cdc.stat[0] = data & BIT_DECEN;
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/* update decoding mode */
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if (data & BIT_AUTORQ)
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{
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/* set MODE bit according to CTRL1 register & clear FORM bit */
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cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ;
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}
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else
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{
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/* set MODE & FORM bits according to CTRL1 register */
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cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ);
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}
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cdc.ctrl[0] = data;
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scd.regs[0x04>>1].byte.l = 0x0b;
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break;
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}
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case 0x0b: /* CTRL1 */
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{
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/* update decoding mode */
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if (cdc.ctrl[0] & BIT_AUTORQ)
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{
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/* set MODE bit according to CTRL1 register & clear FORM bit */
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cdc.stat[2] = data & BIT_MODRQ;
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}
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else
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{
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/* set MODE & FORM bits according to CTRL1 register */
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cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ);
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}
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cdc.ctrl[1] = data;
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scd.regs[0x04>>1].byte.l = 0x0c;
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break;
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}
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case 0x0c: /* PTL */
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cdc.pt.byte.l = data;
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scd.regs[0x04>>1].byte.l = 0x0d;
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break;
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case 0x0d: /* PTH */
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cdc.pt.byte.h = data;
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scd.regs[0x04>>1].byte.l = 0x0e;
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break;
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case 0x0e: /* CTRL2 (unused) */
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scd.regs[0x04>>1].byte.l = 0x0f;
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break;
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case 0x0f: /* RESET */
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cdc_reset();
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break;
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default: /* by default, SBOUT is not used */
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break;
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}
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}
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unsigned char cdc_reg_r(void)
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{
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#ifdef LOG_CDC
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error("CDC register %X read (%X) ", scd.regs[0x04>>1].byte.l & 0x0F, s68k.pc);
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#endif
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switch (scd.regs[0x04>>1].byte.l & 0x0F)
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{
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case 0x01: /* IFSTAT */
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scd.regs[0x04>>1].byte.l = 0x02;
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return cdc.ifstat;
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case 0x02: /* DBCL */
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scd.regs[0x04>>1].byte.l = 0x03;
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return cdc.dbc.byte.l;
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case 0x03: /* DBCH */
|
|
scd.regs[0x04>>1].byte.l = 0x04;
|
|
return cdc.dbc.byte.h;
|
|
|
|
case 0x04: /* HEAD0 */
|
|
scd.regs[0x04>>1].byte.l = 0x05;
|
|
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][0];
|
|
|
|
case 0x05: /* HEAD1 */
|
|
scd.regs[0x04>>1].byte.l = 0x06;
|
|
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][1];
|
|
|
|
case 0x06: /* HEAD2 */
|
|
scd.regs[0x04>>1].byte.l = 0x07;
|
|
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][2];
|
|
|
|
case 0x07: /* HEAD3 */
|
|
scd.regs[0x04>>1].byte.l = 0x08;
|
|
return cdc.head[cdc.ctrl[1] & BIT_SHDREN][3];
|
|
|
|
case 0x08: /* PTL */
|
|
scd.regs[0x04>>1].byte.l = 0x09;
|
|
return cdc.pt.byte.l;
|
|
|
|
case 0x09: /* PTH */
|
|
scd.regs[0x04>>1].byte.l = 0x0a;
|
|
return cdc.pt.byte.h;
|
|
|
|
case 0x0a: /* WAL */
|
|
scd.regs[0x04>>1].byte.l = 0x0b;
|
|
return cdc.wa.byte.l;
|
|
|
|
case 0x0b: /* WAH */
|
|
scd.regs[0x04>>1].byte.l = 0x0c;
|
|
return cdc.wa.byte.h;
|
|
|
|
case 0x0c: /* STAT0 */
|
|
scd.regs[0x04>>1].byte.l = 0x0d;
|
|
return cdc.stat[0];
|
|
|
|
case 0x0d: /* STAT1 (always return 0) */
|
|
scd.regs[0x04>>1].byte.l = 0x0e;
|
|
return 0x00;
|
|
|
|
case 0x0e: /* STAT2 */
|
|
scd.regs[0x04>>1].byte.l = 0x0f;
|
|
return cdc.stat[2];
|
|
|
|
case 0x0f: /* STAT3 */
|
|
{
|
|
uint8 data = cdc.stat[3];
|
|
|
|
/* clear !VALST (note: this is not 100% correct but BIOS do not seem to care) */
|
|
cdc.stat[3] = BIT_VALST;
|
|
|
|
/* clear pending decoder interrupt */
|
|
cdc.ifstat |= BIT_DECI;
|
|
|
|
#if 0
|
|
/* no pending data transfer end interrupt */
|
|
if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
|
|
{
|
|
/* clear pending level 5 interrupt */
|
|
scd.pending &= ~(1 << 5);
|
|
|
|
/* update IRQ level */
|
|
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
|
}
|
|
#endif
|
|
|
|
scd.regs[0x04>>1].byte.l = 0x00;
|
|
return data;
|
|
}
|
|
|
|
default: /* by default, COMIN is always empty */
|
|
return 0xff;
|
|
}
|
|
}
|
|
|
|
unsigned short cdc_host_r(void)
|
|
{
|
|
/* check if data is available */
|
|
if (!(cdc.ifstat & BIT_DTEN))
|
|
{
|
|
/* read data word from CDC RAM buffer */
|
|
uint16 data = *(uint16 *)(cdc.ram + (cdc.dac.w & 0x3ffe));
|
|
|
|
#ifdef LSB_FIRST
|
|
/* source data is stored in big endian format */
|
|
data = ((data >> 8) | (data << 8)) & 0xffff;
|
|
#endif
|
|
|
|
#ifdef LOG_CDC
|
|
error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac.w, data, cdc.dbc.w, s68k.pc);
|
|
#endif
|
|
|
|
/* increment data address counter */
|
|
cdc.dac.w += 2;
|
|
|
|
/* decrement data byte counter */
|
|
cdc.dbc.w -= 2;
|
|
|
|
/* end of transfer ? */
|
|
if ((int16)cdc.dbc.w <= 0)
|
|
{
|
|
/* reset data byte counter (DBCH bits 4-7 should be set to 1) */
|
|
cdc.dbc.w = 0xf000;
|
|
|
|
/* clear !DTEN and !DTBSY */
|
|
cdc.ifstat |= (BIT_DTBSY | BIT_DTEN);
|
|
|
|
/* pending Data Transfer End interrupt */
|
|
cdc.ifstat &= ~BIT_DTEI;
|
|
|
|
/* Data Transfer End interrupt enabled ? */
|
|
if (cdc.ifctrl & BIT_DTEIEN)
|
|
{
|
|
/* pending level 5 interrupt */
|
|
scd.pending |= (1 << 5);
|
|
|
|
/* level 5 interrupt enabled ? */
|
|
if (scd.regs[0x32>>1].byte.l & 0x20)
|
|
{
|
|
/* update IRQ level */
|
|
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
|
}
|
|
}
|
|
|
|
/* clear DSR bit & set EDT bit (SCD register $04) */
|
|
scd.regs[0x04>>1].byte.h = (scd.regs[0x04>>1].byte.h & 0x07) | 0x80;
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
#ifdef LOG_CDC
|
|
error("error reading CDC host (data transfer disabled)\n");
|
|
#endif
|
|
return 0xffff;
|
|
}
|