mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
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306 lines
6.4 KiB
C
306 lines
6.4 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Z80 bank access to 68k bus
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Eke-Eke (2007,2008,2009), additional code & fixes for the GCN/Wii port
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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****************************************************************************************/
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#include "shared.h"
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/*
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Handlers for access to unused addresses and those which make the
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machine lock up.
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*/
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unsigned int zbank_unused_r(unsigned int address)
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{
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#ifdef LOGERROR
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error("Z80 bank unused read %06X (%x)\n", address, Z80.pc.d);
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#endif
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return (address & 1) ? 0x00 : 0xFF;
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}
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void zbank_unused_w(unsigned int address, unsigned int data)
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{
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#ifdef LOGERROR
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error("Z80 bank unused write %06X = %02X\n", address, data);
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#endif
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}
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unsigned int zbank_lockup_r(unsigned int address)
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{
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#ifdef LOGERROR
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error("Z80 bank lockup read %06X (%x)\n", address, Z80.pc.d);
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#endif
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if (!config.force_dtack)
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{
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mcycles_z80 = 0xFFFFFFFF;
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zstate = 0;
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}
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return 0xFF;
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}
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void zbank_lockup_w(unsigned int address, unsigned int data)
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{
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#ifdef LOGERROR
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error("Z80 bank lockup write %06X = %02X (%x)\n", address, data, Z80.pc.d);
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#endif
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if (!config.force_dtack)
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{
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mcycles_z80 = 0xFFFFFFFF;
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zstate = 0;
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}
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}
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/* I/O & Control registers */
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unsigned int zbank_read_ctrl_io(unsigned int address)
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{
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switch ((address >> 8) & 0xFF)
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{
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case 0x00: /* I/O chip */
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{
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if (!(address & 0xE0))
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{
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return (io_68k_read((address >> 1) & 0x0F));
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}
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return zbank_unused_r(address);
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}
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case 0x11: /* BUSACK */
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{
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if (address & 1)
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{
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return zbank_unused_r(address);
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}
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return 0xFF;
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}
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case 0x30: /* TIME */
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{
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if (cart.hw.time_r)
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{
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unsigned int data = cart.hw.time_r(address);
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if (address & 1)
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{
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return (data & 0xFF);
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}
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return (data >> 8);
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}
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return zbank_unused_r(address);
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}
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case 0x41: /* OS ROM */
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{
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if (address & 1)
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{
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return (gen_bankswitch_r() | 0xFE);
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}
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return zbank_unused_r(address);
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}
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case 0x10: /* MEMORY MODE */
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case 0x12: /* RESET */
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case 0x20: /* MEGA-CD */
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case 0x40: /* TMSS */
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case 0x44: /* RADICA */
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case 0x50: /* SVP REGISTERS */
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{
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return zbank_unused_r(address);
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}
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default: /* Invalid address */
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{
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return zbank_lockup_r(address);
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}
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}
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}
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void zbank_write_ctrl_io(unsigned int address, unsigned int data)
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{
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switch ((address >> 8) & 0xFF)
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{
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case 0x00: /* I/O chip */
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{
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/* get /LWR only */
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if ((address & 0xE1) == 0x01)
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{
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io_68k_write((address >> 1) & 0x0F, data);
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return;
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}
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zbank_unused_w(address, data);
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return;
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}
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case 0x11: /* BUSREQ */
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{
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if (!(address & 1))
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{
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gen_zbusreq_w(data & 1, mcycles_z80);
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return;
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}
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zbank_unused_w(address, data);
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return;
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}
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case 0x12: /* RESET */
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{
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if (!(address & 1))
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{
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gen_zreset_w(data & 1, mcycles_z80);
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return;
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}
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zbank_unused_w(address, data);
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return;
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}
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case 0x30: /* TIME */
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{
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cart.hw.time_w(address, data);
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return;
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}
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case 0x41: /* OS ROM */
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{
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if (address & 1)
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{
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gen_bankswitch_w(data & 1);
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return;
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}
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zbank_unused_w(address, data);
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return;
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}
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case 0x10: /* MEMORY MODE */
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case 0x20: /* MEGA-CD */
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case 0x40: /* TMSS */
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case 0x44: /* RADICA */
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case 0x50: /* SVP REGISTERS */
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{
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zbank_unused_w(address, data);
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return;
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}
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default: /* Invalid address */
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{
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zbank_lockup_w(address, data);
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return;
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}
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}
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}
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/* VDP */
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unsigned int zbank_read_vdp(unsigned int address)
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{
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switch (address & 0xFD)
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{
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case 0x00: /* DATA */
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{
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return (vdp_68k_data_r() >> 8);
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}
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case 0x01: /* DATA */
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{
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return (vdp_68k_data_r() & 0xFF);
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}
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case 0x04: /* CTRL */
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{
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return (((vdp_ctrl_r(mcycles_z80) >> 8) & 3) | 0xFC);
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}
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case 0x05: /* CTRL */
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{
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return (vdp_ctrl_r(mcycles_z80) & 0xFF);
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}
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case 0x08: /* HVC */
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case 0x0C:
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{
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return (vdp_hvc_r(mcycles_z80) >> 8);
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}
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case 0x09: /* HVC */
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case 0x0D:
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{
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return (vdp_hvc_r(mcycles_z80) & 0xFF);
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}
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case 0x18: /* Unused */
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case 0x19:
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case 0x1C:
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case 0x1D:
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{
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return zbank_unused_r(address);
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}
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default: /* Invalid address */
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{
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return zbank_lockup_r(address);
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}
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}
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}
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void zbank_write_vdp(unsigned int address, unsigned int data)
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{
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switch (address & 0xFC)
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{
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case 0x00: /* Data port */
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{
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vdp_68k_data_w(data << 8 | data);
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return;
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}
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case 0x04: /* Control port */
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{
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vdp_68k_ctrl_w(data << 8 | data);
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return;
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}
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case 0x10: /* PSG */
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case 0x14:
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{
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if (address & 1)
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{
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psg_write(mcycles_z80, data);
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return;
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}
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zbank_unused_w(address, data);
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return;
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}
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case 0x18: /* Unused */
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{
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zbank_unused_w(address, data);
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return;
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}
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case 0x1C: /* TEST register */
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{
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vdp_test_w(data << 8 | data);
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return;
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}
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default: /* Invalid address */
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{
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zbank_lockup_w(address, data);
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return;
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}
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}
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}
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