mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
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373 lines
11 KiB
C
373 lines
11 KiB
C
/***************************************************************************************
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* Genesis Plus
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* Genesis internals & Bus controller
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Eke-Eke (2007,2008,2009), additional code & fixes for the GCN/Wii port
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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****************************************************************************************/
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#include "shared.h"
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uint8 tmss[4]; /* TMSS security register */
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uint8 bios_rom[0x800]; /* OS ROM */
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uint8 work_ram[0x10000]; /* 68K RAM */
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uint8 zram[0x2000]; /* Z80 RAM */
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uint32 zbank; /* Z80 bank window address */
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uint8 zstate; /* Z80 bus state (d0 = BUSACK, d1 = /RESET) */
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/* PICO data */
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uint8 pico_current;
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uint8 pico_page[7];
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void gen_init(void)
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{
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int i;
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/* initialize CPUs */
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m68k_set_cpu_type(M68K_CPU_TYPE_68000);
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m68k_init();
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z80_init(0,z80_irq_callback);
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/* initialize 68k mapped memory */
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/* $000000-$7fffff is affected to cartridge area (see cart_hw.c) */
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/* $800000-$ffffff is affected to WRAM (see VDP DMA) */
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for (i=0x80; i<0x100; i++)
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{
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m68k_memory_map[i].base = work_ram;
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m68k_memory_map[i].read8 = NULL;
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m68k_memory_map[i].read16 = NULL;
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m68k_memory_map[i].write8 = NULL;
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m68k_memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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/* initialize 68k memory handlers */
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for (i=0x80; i<0xe0; i++)
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{
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/* illegal area */
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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/* Z80 bus (bank access) */
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zbank_memory_map[0xa0].read = zbank_lockup_r;
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zbank_memory_map[0xa0].write = zbank_lockup_w;
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/* I/O & Control registers */
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m68k_memory_map[0xa1].read8 = ctrl_io_read_byte;
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m68k_memory_map[0xa1].read16 = ctrl_io_read_word;
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m68k_memory_map[0xa1].write8 = ctrl_io_write_byte;
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m68k_memory_map[0xa1].write16 = ctrl_io_write_word;
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zbank_memory_map[0xa1].read = zbank_read_ctrl_io;
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zbank_memory_map[0xa1].write = zbank_write_ctrl_io;
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/* VDP (initially locked on models with TMSS) */
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if (!(config.tmss & 1))
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{
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = vdp_read_byte;
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m68k_memory_map[i].read16 = vdp_read_word;
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m68k_memory_map[i].write8 = vdp_write_byte;
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m68k_memory_map[i].write16 = vdp_write_word;
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zbank_memory_map[i].read = zbank_read_vdp;
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zbank_memory_map[i].write = zbank_write_vdp;
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}
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}
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/* SEGA PICO */
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if (system_hw == SYSTEM_PICO)
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{
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m68k_memory_map[0x80].read8 = pico_read_byte;
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m68k_memory_map[0x80].read16 = pico_read_word;
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m68k_memory_map[0x80].write8 = m68k_unused_8_w;
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m68k_memory_map[0x80].write16 = m68k_unused_16_w;
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/* there is no I/O area (Notaz) */
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m68k_memory_map[0xa1].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa1].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa1].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa1].write16 = m68k_unused_16_w;
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/* page registers */
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pico_current = 0x00;
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pico_page[0] = 0x00;
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pico_page[1] = 0x01;
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pico_page[2] = 0x03;
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pico_page[3] = 0x07;
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pico_page[4] = 0x0F;
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pico_page[5] = 0x1F;
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pico_page[6] = 0x3F;
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}
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}
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void gen_hardreset(void)
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{
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/* Clear RAM */
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memset (work_ram, 0x00, sizeof (work_ram));
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memset (zram, 0x00, sizeof (zram));
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/* TMSS + OS ROM support */
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memset(tmss, 0x00, sizeof(tmss));
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if (config.tmss == 3)
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{
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m68k_memory_map[0].base = bios_rom;
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}
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/* 68k & Z80 could restart anywhere in VDP frame (Bonkers, Eternal Champions, X-Men 2) */
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mcycles_68k = mcycles_z80 = (uint32)((MCYCLES_PER_LINE * lines_per_frame) * ((double)rand() / (double)RAND_MAX));
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/* Z80 bus is released & Z80 is stopped */
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m68k_memory_map[0xa0].read8 = m68k_read_bus_8;
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m68k_memory_map[0xa0].read16 = m68k_read_bus_16;
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m68k_memory_map[0xa0].write8 = m68k_unused_8_w;
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m68k_memory_map[0xa0].write16 = m68k_unused_16_w;
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zstate = 0;
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/* Assume default bank is $000000-$007FFF */
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zbank = 0;
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/* Reset 68k, Z80 & YM2612 */
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m68k_pulse_reset();
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z80_reset();
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YM2612ResetChip();
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}
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void gen_softreset(int state)
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{
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if (state)
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{
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/* Halt 68k, Z80 & YM2612 */
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m68k_pulse_halt();
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zstate = 0;
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YM2612ResetChip();
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}
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else
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{
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/* Reset PRO Action Replay (if switch is in TRAINER position) */
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if (areplay_get_status() == AR_SWITCH_TRAINER)
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{
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areplay_reset(0);
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}
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/* 68k & Z80 could restart anywhere in VDP frame (Bonkers, Eternal Champions, X-Men 2) */
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mcycles_68k = mcycles_z80 = (uint32)((MCYCLES_PER_LINE * lines_per_frame) * ((double)rand() / (double)RAND_MAX));
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/* Reset 68k, Z80 & YM2612 */
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m68k_pulse_reset();
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z80_reset();
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YM2612ResetChip();
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}
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}
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void gen_shutdown(void)
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{
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z80_exit();
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}
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/*-----------------------------------------------------------------------
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OS ROM / TMSS register control functions
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-----------------------------------------------------------------------*/
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void gen_tmss_w(unsigned int offset, unsigned int data)
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{
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/* write TMSS regisiter */
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WRITE_WORD(tmss, offset, data);
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/* VDP requires "SEGA" value to be written in TMSSS register */
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int i;
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if (strncmp((char *)tmss, "SEGA", 4) == 0)
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{
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = vdp_read_byte;
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m68k_memory_map[i].read16 = vdp_read_word;
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m68k_memory_map[i].write8 = vdp_write_byte;
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m68k_memory_map[i].write16 = vdp_write_word;
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zbank_memory_map[i].read = zbank_read_vdp;
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zbank_memory_map[i].write = zbank_write_vdp;
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}
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}
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else
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{
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for (i=0xc0; i<0xe0; i+=8)
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{
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m68k_memory_map[i].read8 = m68k_lockup_r_8;
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m68k_memory_map[i].read16 = m68k_lockup_r_16;
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m68k_memory_map[i].write8 = m68k_lockup_w_8;
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m68k_memory_map[i].write16 = m68k_lockup_w_16;
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zbank_memory_map[i].read = zbank_lockup_r;
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zbank_memory_map[i].write = zbank_lockup_w;
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}
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}
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}
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void gen_bankswitch_w(unsigned int data)
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{
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/* BIOS has not been loaded yet */
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if (!(config.tmss & 2))
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{
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config.tmss |= 2;
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memcpy(bios_rom, cart.rom, 0x800);
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memset(cart.rom, 0xff, cart.romsize);
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}
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if (data & 1)
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{
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/* enable CART */
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m68k_memory_map[0].base = cart.base;
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}
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else
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{
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/* enable internal BIOS ROM */
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m68k_memory_map[0].base = bios_rom;
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}
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}
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unsigned int gen_bankswitch_r(void)
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{
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return (m68k_memory_map[0].base == cart.base);
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}
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/*-----------------------------------------------------------------------
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Z80 Bus controller chip functions
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-----------------------------------------------------------------------*/
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void gen_zbusreq_w(unsigned int data, unsigned int cycles)
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{
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if (data) /* !ZBUSREQ asserted */
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{
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/* check if Z80 is going to be stopped */
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if (zstate == 1)
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{
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/* resynchronize with 68k */
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z80_run(cycles);
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/* enable 68k access to Z80 bus */
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_m68k_memory_map *base = &m68k_memory_map[0xa0];
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base->read8 = z80_read_byte;
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base->read16 = z80_read_word;
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base->write8 = z80_write_byte;
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base->write16 = z80_write_word;
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}
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/* update Z80 bus status */
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zstate |= 2;
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}
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else /* !ZBUSREQ released */
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{
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/* check if Z80 is going to be restarted */
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if (zstate == 3)
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{
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/* resynchronize with 68k */
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mcycles_z80 = cycles;
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/* disable 68k access to Z80 bus */
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_m68k_memory_map *base = &m68k_memory_map[0xa0];
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base->read8 = m68k_read_bus_8;
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base->read16 = m68k_read_bus_16;
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base->write8 = m68k_unused_8_w;
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base->write16 = m68k_unused_16_w;
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}
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/* update Z80 bus status */
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zstate &= 1;
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}
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}
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void gen_zreset_w(unsigned int data, unsigned int cycles)
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{
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if (data) /* !ZRESET released */
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{
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/* check if Z80 is going to be restarted */
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if (zstate == 0)
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{
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/* resynchronize with 68k */
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mcycles_z80 = cycles;
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/* reset Z80 & YM2612 */
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z80_reset();
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fm_reset(cycles);
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}
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/* check if 68k access to Z80 bus is granted */
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else if (zstate == 2)
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{
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/* enable 68k access to Z80 bus */
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_m68k_memory_map *base = &m68k_memory_map[0xa0];
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base->read8 = z80_read_byte;
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base->read16 = z80_read_word;
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base->write8 = z80_write_byte;
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base->write16 = z80_write_word;
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/* reset Z80 & YM2612 */
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z80_reset();
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fm_reset(cycles);
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}
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/* update Z80 bus status */
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zstate |= 1;
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}
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else /* !ZRESET asserted */
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{
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/* check if Z80 is going to be stopped */
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if (zstate == 1)
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{
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/* resynchronize with 68k */
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z80_run(cycles);
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}
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/* check if 68k had access to Z80 bus */
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else if (zstate == 3)
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{
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/* disable 68k access to Z80 bus */
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_m68k_memory_map *base = &m68k_memory_map[0xa0];
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base->read8 = m68k_read_bus_8;
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base->read16 = m68k_read_bus_16;
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base->write8 = m68k_unused_8_w;
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base->write16 = m68k_unused_16_w;
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}
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/* stop YM2612 */
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fm_reset(cycles);
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/* update Z80 bus status */
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zstate &= 2;
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}
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}
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void gen_zbank_w (unsigned int data)
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{
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zbank = ((zbank >> 1) | ((data & 1) << 23)) & 0xFF8000;
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}
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int z80_irq_callback (int param)
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{
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return 0xFF;
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}
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