mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-10 04:45:08 +01:00
597 lines
16 KiB
C
597 lines
16 KiB
C
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#include "shared.h"
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#include "hvc.h"
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/* Pack and unpack CRAM data */
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#define PACK_CRAM(d) ((((d)&0xE00)>>9)|(((d)&0x0E0)>>2)|(((d)&0x00E)<<5))
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#define UNPACK_CRAM(d) ((((d)&0x1C0)>>5)|((d)&0x038)<<2|(((d)&0x007)<<9))
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/* Mark a pattern as dirty */
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#define MARK_BG_DIRTY(addr) \
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{ \
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int name = (addr >> 5) & 0x7FF; \
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if(bg_name_dirty[name] == 0) bg_name_list[bg_list_index++] = name; \
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bg_name_dirty[name] |= (1 << ((addr >> 2) & 0x07)); \
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}
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/* Tables that define the playfield layout */
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uint8 shift_table[] = { 6, 7, 0, 8 };
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uint8 col_mask_table[] = { 0x0F, 0x1F, 0x0F, 0x3F };
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uint16 row_mask_table[] = { 0x0FF, 0x1FF, 0x2FF, 0x3FF };
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uint32 y_mask_table[] = { 0x1FC0, 0x1F80, 0x1FC0, 0x1F00 };
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/* DMA Timings Table
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DMA Mode Width Display Transfer Count
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-----------------------------------------------------
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68K > VDP 32-cell Active 16
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Blanking 167
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40-cell Active 18
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Blanking 205
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VRAM Fill 32-cell Active 15
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Blanking 166
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40-cell Active 17
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Blanking 204
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VRAM Copy 32-cell Active 8
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Blanking 83
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40-cell Active 9
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Blanking 102
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*/
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uint8 dmarate_table[16] = {
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83 , 102, 8, 9, // M68k to VRAM
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167, 205, 16, 18, // M68k to VSRAM or CRAM
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166, 204, 15, 17, // DMA fill
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83 , 102, 8, 9 // DMA Copy
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};
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uint8 sat[0x400]; /* Internal copy of sprite attribute table */
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uint8 vram[0x10000]; /* Video RAM (64Kx8) */
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uint8 cram[0x80]; /* On-chip color RAM (64x9) */
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uint8 vsram[0x80]; /* On-chip vertical scroll RAM (40x11) */
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uint8 reg[0x20]; /* Internal VDP registers (23x8) */
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uint16 addr; /* Address register */
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uint16 addr_latch; /* Latched A15, A14 of address */
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uint8 code; /* Code register */
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uint8 pending; /* Pending write flag */
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uint16 status; /* VDP status flags */
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uint16 ntab; /* Name table A base address */
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uint16 ntbb; /* Name table B base address */
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uint16 ntwb; /* Name table W base address */
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uint16 satb; /* Sprite attribute table base address */
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uint16 hscb; /* Horizontal scroll table base address */
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uint16 sat_base_mask; /* Base bits of SAT */
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uint16 sat_addr_mask; /* Index bits of SAT */
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uint8 border; /* Border color index */
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uint8 bg_name_dirty[0x800]; /* 1= This pattern is dirty */
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uint16 bg_name_list[0x800]; /* List of modified pattern indices */
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uint16 bg_list_index; /* # of modified patterns in list */
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uint8 bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
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uint8 playfield_shift; /* Width of planes A, B (in bits) */
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uint8 playfield_col_mask; /* Vertical scroll mask */
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uint16 playfield_row_mask; /* Horizontal scroll mask */
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uint32 y_mask; /* Name table Y-index bits mask */
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uint8 hint_pending; /* 0= Line interrupt is pending */
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uint8 vint_pending; /* 1= Frame interrupt is pending */
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int16 h_counter; /* Raster counter */
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int16 hc_latch; /* latched HCounter (INT2) */
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uint16 v_counter; /* VDP scan line counter */
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uint8 im2_flag; /* 1= Interlace mode 2 is being used */
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uint16 frame_end; /* End-of-frame (IRQ line) */
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uint8 dmafill; /* 1= DMA fill has been requested */
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uint32 dma_endCycles; /* DMA ending cycles count */
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uint8 vdp_pal = 0 ; /* CPU mode (NTSC by default) */
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uint8 vdp_rate = 60; /* CPU speed (60Hz by default)*/
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void (*color_update) (int index, uint16 data);
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uint8 dmatiming = 1;
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uint8 vdptiming = 1;
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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/*--------------------------------------------------------------------------*/
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void vdp_init (void)
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{}
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void vdp_reset (void)
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{
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memset ((char *) sat, 0, sizeof (sat));
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memset ((char *) vram, 0, sizeof (vram));
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memset ((char *) cram, 0, sizeof (cram));
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memset ((char *) vsram, 0, sizeof (vsram));
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memset ((char *) reg, 0, sizeof (reg));
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addr = addr_latch = code = pending = 0;
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ntab = ntbb = ntwb = satb = hscb = 0;
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sat_base_mask = 0xFE00;
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sat_addr_mask = 0x01FF;
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/* Mark all colors as dirty to force a palette update */
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border = 0x00;
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memset ((char *) bg_name_dirty, 0, sizeof (bg_name_dirty));
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memset ((char *) bg_name_list, 0, sizeof (bg_name_list));
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bg_list_index = 0;
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memset ((char *) bg_pattern_cache, 0, sizeof (bg_pattern_cache));
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playfield_shift = 6;
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playfield_col_mask = 0x0F;
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playfield_row_mask = 0x0FF;
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y_mask = 0x1FC0;
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hint_pending = vint_pending = 0;
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h_counter = 0;
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hc_latch = -1;
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v_counter = 0;
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dmafill = 0;
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im2_flag = 0;
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frame_end = 0xE0;
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dma_endCycles = 0;
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status = 0x200; /* fifo empty - all other flags clear */
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/* Initialize viewport */
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bitmap.viewport.x = 0x20;
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bitmap.viewport.y = 0x20;
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bitmap.viewport.w = 256;
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bitmap.viewport.h = 224;
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bitmap.viewport.oh = 256;
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bitmap.viewport.ow = 224;
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bitmap.viewport.changed = 1;
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}
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void vdp_shutdown (void)
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{}
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/*--------------------------------------------------------------------------*/
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/* DMA Operations */
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/*--------------------------------------------------------------------------*/
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/* DMA Timings */
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/* timing type = 0 (Copy to VRAM), 1 (Copy to VSRAM or CRAM), 2 (VRAM Fill), 3 (VRAM Copy) */
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void dma_update(int type, int length)
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{
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uint32 dma_cycles;
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uint8 index = 4 * type; /* DMA timing type */
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if (!dmatiming) return;
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/* get the appropriate tranfer rate (bytes/line) for this DMA operation */
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if (!(status&8) && (reg[1]&0x40)) index += 2; /* not in VBLANK and Display ON */
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index += (reg[12] & 1); /* 32 or 40 Horizontal Cells */
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/* determinate associated 68kcycles number */
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dma_cycles = (misc68Kcycles * length ) / dmarate_table[index];
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if (type < 2)
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{
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/* 68K COPY to V-RAM */
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/* 68K is frozen during DMA operation */
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m68k_freeze(dma_cycles);
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}
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else
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{
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/* VRAM Fill or VRAM Copy */
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/* we keep the number of cycles executed so far */
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/* used for DMA Busy flag update on status read */
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dma_endCycles = count_m68k + m68k_cycles_run() + dma_cycles;
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dma_m68k = 0;
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/* set DMA Busy flag */
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status |= 0x0002;
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}
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}
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/* VRAM to VRAM copy
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Read byte from VRAM (source), write to VRAM (addr),
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bump source and add r15 to addr.
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- see how source addr is affected
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(can it make high source byte inc?) */
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void dma_copy (void)
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{
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int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
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if (!length) length = 0x10000;
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dma_update(3,length);
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do
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{
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vram[addr] = vram[source];
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MARK_BG_DIRTY (addr);
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source = (source + 1) & 0xFFFF;
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addr += reg[15];
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}
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while (--length);
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reg[19] = length & 0xFF;
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reg[20] = (length >> 8) & 0xFF;
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reg[21] = source & 0xFF; /* not sure */
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reg[22] = (source >> 8) & 0xFF;
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}
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/* 68K Copy to VRAM, VSRAM or CRAM */
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void dma_vbus (void)
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{
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uint32 base, source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
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uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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uint8 old_vdptiming = vdptiming;
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if (!length) length = 0x10000;
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base = source;
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/* DMA timings */
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if ((code & 0x0F) == 0x01) dma_update(0,length); /* VRAM */
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else dma_update(1,length); /* CRAM & VSRAM */
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vdptiming = 0;
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do
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{
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uint16 temp = vdp_dma_r (source);
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source += 2;
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source = ((base & 0xFE0000) | (source & 0x1FFFF));
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vdp_data_w (temp);
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}
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while (--length);
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vdptiming = old_vdptiming;
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reg[19] = length & 0xFF;
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reg[20] = (length >> 8) & 0xFF;
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reg[21] = (source >> 1) & 0xFF;
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reg[22] = (source >> 9) & 0xFF;
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reg[23] = (reg[23] & 0x80) | ((source >> 17) & 0x7F);
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}
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/* VRAM FILL */
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void dma_fill(uint16 data)
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{
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int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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if (!length) length = 0x10000;
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dma_update(2, length);
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WRITE_BYTE(vram, addr, data & 0xFF);
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do
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{
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WRITE_BYTE(vram, addr^1, (data >> 8) & 0xFF);
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MARK_BG_DIRTY (addr);
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addr += reg[15];
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}
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while (--length);
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reg[19] = length & 0xFF;
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reg[20] = (length >> 8) & 0xFF;
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dmafill = 0;
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}
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/*--------------------------------------------------------------------------*/
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/* Memory access functions */
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/*--------------------------------------------------------------------------*/
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void vdp_ctrl_w (uint16 data)
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{
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if (pending == 0)
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{
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if ((data & 0xC000) == 0x8000)
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{
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uint8 r = (data >> 8) & 0x1F;
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uint8 d = data & 0xFF;
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vdp_reg_w (r, d);
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}
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else pending = 1;
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addr = ((addr_latch & 0xC000) | (data & 0x3FFF)) & 0xFFFF;
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code = ((code & 0x3C) | ((data >> 14) & 0x03)) & 0x3F;
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}
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else
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{
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/* Clear pending flag */
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pending = 0;
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/* Update address and code registers */
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addr = ((addr & 0x3FFF) | ((data & 3) << 14)) & 0xFFFF;
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code = ((code & 0x03) | ((data >> 2) & 0x3C)) & 0x3F;
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/* Save address bits A15 and A14 */
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addr_latch = (addr & 0xC000);
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if ((code & 0x20) && (reg[1] & 0x10))
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{
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switch (reg[23] & 0xC0)
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{
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case 0x00: /* V bus to VDP DMA */
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case 0x40: /* V bus to VDP DMA */
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dma_vbus ();
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break;
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case 0x80: /* VRAM fill */
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dmafill = 1;
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break;
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case 0xC0: /* VRAM copy */
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dma_copy ();
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break;
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}
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}
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}
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}
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uint16 vdp_ctrl_r (void)
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{
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/**
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* Return vdp status
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*
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* Bits are
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* 0 0:1 ntsc:pal
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* 1 DMA Busy
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* 2 During HBlank
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* 3 During VBlank
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* 4 Frame Interlace 0:even 1:odd
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* 5 Sprite collision
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* 6 Too many sprites per line
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* 7 v interrupt occurred
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* 8 Write FIFO full
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* 9 Write FIFO empty
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* 10 - 15 Next word on bus
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*/
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uint16 temp;
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int dma_lastCycles = dma_endCycles - (dma_m68k + count_m68k + m68k_cycles_run());
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/* reset DMA status flag if needed */
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if ((status & 0x0002) && (dma_lastCycles <= 0)) status &= 0xFFFD;
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temp = status | vdp_pal;
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pending = 0;
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/* reset status */
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status ^= 0xFF00; /* toggle FIFO status & new word on bus */
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status &= 0xFF9F; /* clear sprite overflow & sprite collision */
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if (!(status & 8)) status &= ~0x0080; /* not in VBLANK: clear vint flag */
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if (!(reg[1] & 0x40)) temp |= 0x8; /* no display => in VBLANK*/
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return (temp);
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}
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void vdp_data_w (uint16 data)
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{
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/* Clear pending flag */
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pending = 0;
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if (dmafill)
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{
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dma_fill(data);
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return;
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}
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/* delays VDP RAM access */
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/* hack for Chaos Engine / Soldiers of Fortune */
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if (vdptiming && !(status&8) && (reg[1]&0x40))
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{
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if (reg[12] & 1) m68k_freeze(30); // 40 cell
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else m68k_freeze(27); // 32 cell
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}
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switch (code & 0x0F)
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{
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case 0x01: /* VRAM */
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/* Byte-swap data if A0 is set */
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if (addr & 1) data = (data >> 8) | (data << 8);
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/* Copy SAT data to the internal SAT */
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if ((addr & sat_base_mask) == satb)
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{
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*(uint16 *) & sat[addr & sat_addr_mask] = data;
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}
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/* Only write unique data to VRAM */
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if (data != *(uint16 *) & vram[addr & 0xFFFE])
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{
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/* Write data to VRAM */
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*(uint16 *) & vram[addr & 0xFFFE] = data;
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/* Update the pattern cache */
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MARK_BG_DIRTY (addr);
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}
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break;
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case 0x03: /* CRAM */
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{
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uint16 *p = (uint16 *) & cram[(addr & 0x7E)];
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data = PACK_CRAM (data & 0x0EEE);
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if (data != *p)
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{
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int index = (addr >> 1) & 0x3F;
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*p = data;
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color_update (index, *p);
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color_update (0x00, *(uint16 *)&cram[border << 1]);
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}
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}
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break;
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case 0x05: /* VSRAM */
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*(uint16 *) & vsram[(addr & 0x7E)] = data;
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break;
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}
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/* Bump address register */
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addr += reg[15];
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}
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uint16 vdp_data_r (void)
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{
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uint16 temp = 0;
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/* Clear pending flag */
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pending = 0;
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switch (code & 0x0F)
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{
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case 0x00: /* VRAM */
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temp = *(uint16 *) & vram[(addr & 0xFFFE)];
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break;
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case 0x08: /* CRAM */
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temp = *(uint16 *) & cram[(addr & 0x7E)];
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temp = UNPACK_CRAM (temp);
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break;
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case 0x04: /* VSRAM */
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temp = *(uint16 *) & vsram[(addr & 0x7E)];
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break;
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}
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/* Bump address register */
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addr += reg[15];
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/* return data */
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return (temp);
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}
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/*
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The reg[] array is updated at the *end* of this function, so the new
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register data can be compared with the previous data.
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*/
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void vdp_reg_w (uint8 r, uint8 d)
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{
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switch (r)
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{
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case 0x00: /* CTRL #1 */
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if (!(d & 0x02)) hc_latch = -1;
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break;
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case 0x01: /* CTRL #2 */
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/* Change the frame timing */
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frame_end = (d & 8) ? 0xF0 : 0xE0;
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/* Check if the viewport height has actually been changed */
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if ((reg[1] & 8) != (d & 8))
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{
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/* Update the height of the viewport */
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bitmap.viewport.oh = bitmap.viewport.h;
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bitmap.viewport.h = (d & 8) ? 240 : 224;
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bitmap.viewport.changed = 1;
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}
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break;
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case 0x02: /* NTAB */
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ntab = (d << 10) & 0xE000;
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break;
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case 0x03: /* NTWB */
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ntwb = (d << 10) & ((reg[12] & 1) ? 0xF000 : 0xF800);
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break;
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case 0x04: /* NTBB */
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ntbb = (d << 13) & 0xE000;
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break;
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case 0x05: /* SATB */
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sat_base_mask = (reg[12] & 1) ? 0xFC00 : 0xFE00;
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sat_addr_mask = (reg[12] & 1) ? 0x03FF : 0x01FF;
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satb = (d << 9) & sat_base_mask;
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break;
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case 0x07:
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d &= 0x3F;
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/* Check if the border color has actually changed */
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if (border != d)
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{
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/* Mark the border color as modified */
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border = d;
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color_update (0x00, *(uint16 *) & cram[(border << 1)]);
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}
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break;
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case 0x0C:
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/* Check if the viewport width has actually been changed */
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if ((reg[0x0C] & 1) != (d & 1))
|
|
{
|
|
/* Update the width of the viewport */
|
|
bitmap.viewport.ow = bitmap.viewport.w;
|
|
bitmap.viewport.w = (d & 1) ? 320 : 256;
|
|
bitmap.viewport.changed = 1;
|
|
}
|
|
|
|
/* See if the S/TE mode bit has changed */
|
|
if ((reg[0x0C] & 8) != (d & 8))
|
|
{
|
|
int i;
|
|
reg[0x0C] = d;
|
|
|
|
/* Update colors */
|
|
for (i = 0; i < 0x40; i += 1) color_update (i, *(uint16 *) & cram[i << 1]);
|
|
color_update (0x00, *(uint16 *) & cram[border << 1]);
|
|
}
|
|
|
|
/* Check interlace mode 2 setting */
|
|
im2_flag = ((d & 0x06) == 0x06) ? 1 : 0;
|
|
|
|
/* The following register updates check this value */
|
|
reg[0x0C] = d;
|
|
|
|
/* Update display-dependant registers */
|
|
vdp_reg_w (0x03, reg[0x03]);
|
|
vdp_reg_w (0x05, reg[0x05]);
|
|
break;
|
|
|
|
case 0x0D: /* HSCB */
|
|
hscb = (d << 10) & 0xFC00;
|
|
break;
|
|
|
|
case 0x10: /* Playfield size */
|
|
playfield_shift = shift_table[(d & 3)];
|
|
playfield_col_mask = col_mask_table[(d & 3)];
|
|
playfield_row_mask = row_mask_table[(d >> 4) & 3];
|
|
y_mask = y_mask_table[(d & 3)];
|
|
break;
|
|
}
|
|
|
|
/* Write new register value */
|
|
reg[r] = d;
|
|
}
|
|
|
|
|
|
uint16 vdp_hvc_r (void)
|
|
{
|
|
int cycles = (count_m68k + m68k_cycles_run ()) % misc68Kcycles;
|
|
uint8 *hctab = (reg[12] & 1) ? cycle2hc40 : cycle2hc32;
|
|
uint16 *vctab = (vdp_pal) ? vc_pal_224 : vc_ntsc_224;
|
|
if ((reg[1] & 8) && vdp_pal) vctab = vc_pal_240;
|
|
|
|
uint8 hc = (hc_latch == -1) ? hctab[cycles] : (hc_latch&0xFF);
|
|
|
|
uint16 vc = vctab[v_counter];
|
|
|
|
/* interlace mode 2 */
|
|
if (im2_flag) vc = (vc & 0xFE) | ((vc >> 8) & 0x01);
|
|
|
|
return (((vc << 8)&0xFF00) | hc);
|
|
}
|
|
|
|
|
|
void vdp_test_w (uint16 value)
|
|
{}
|
|
|
|
int vdp_int_ack_callback (int int_level)
|
|
{
|
|
if (vint_pending) vint_pending = 0;
|
|
else hint_pending = 0;
|
|
if (!hint_pending && !vint_pending) m68k_set_irq(0);
|
|
return M68K_INT_ACK_AUTOVECTOR;
|
|
}
|