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Maschell
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@ -27,10 +27,6 @@ The loader will fallback to the default PowerPC processor if the Gekko/Broadway
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## Usage
|
## Usage
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- Choose the `Gekko/Broadway/Espresso` language if asked
|
- Choose the `Gekko/Broadway/Espresso` language if asked
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|
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# Eclipse
|
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|
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To be able open this module in eclipse, you need to create a new Ghidra Module and copy the `.classpath`, `.project` and `.settings` to the root of this repository.
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# Credits
|
# Credits
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- Based on https://github.com/Relys/rpl2elf
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- Based on https://github.com/Relys/rpl2elf
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@ -99,7 +99,12 @@ buildExtension {
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exclude 'certification.manifest'
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exclude 'certification.manifest'
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exclude 'dist/**'
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exclude 'dist/**'
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exclude 'bin/**'
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exclude 'bin/**'
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|
exclude 'lib/**'
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|
exclude 'gradle/**'
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exclude 'src/**'
|
exclude 'src/**'
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|
exclude '.git/**'
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||||||
|
exclude '.idea/**'
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||||||
|
exclude '.github/**'
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exclude '.gradle/**'
|
exclude '.gradle/**'
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exclude 'gradle/**'
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exclude 'gradle/**'
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exclude 'gradlew'
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exclude 'gradlew'
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@ -119,6 +124,8 @@ buildExtension {
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}
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}
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}
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}
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|
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tasks.withType(Copy).all { duplicatesStrategy 'exclude' }
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|
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jar {
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jar {
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duplicatesStrategy(DuplicatesStrategy.EXCLUDE)
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duplicatesStrategy(DuplicatesStrategy.EXCLUDE)
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}
|
}
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201
data/LICENSE
Normal file
201
data/LICENSE
Normal file
@ -0,0 +1,201 @@
|
|||||||
|
Apache License
|
||||||
|
Version 2.0, January 2004
|
||||||
|
http://www.apache.org/licenses/
|
||||||
|
|
||||||
|
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||||
|
|
||||||
|
1. Definitions.
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||||||
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|
||||||
|
"License" shall mean the terms and conditions for use, reproduction,
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|
and distribution as defined by Sections 1 through 9 of this document.
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||||||
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|
"Licensor" shall mean the copyright owner or entity authorized by
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|
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||||||
|
"Legal Entity" shall mean the union of the acting entity and all
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|
"control" means (i) the power, direct or indirect, to cause the
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"You" (or "Your") shall mean an individual or Legal Entity
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END OF TERMS AND CONDITIONS
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APPENDIX: How to apply the Apache License to your work.
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To apply the Apache License to your work, attach the following
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50
data/buildLanguage.xml
Normal file
50
data/buildLanguage.xml
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
|
||||||
|
<!--
|
||||||
|
+ Compile sleigh languages within this module.
|
||||||
|
+ Sleigh compiler options are read from the sleighArgs.txt file.
|
||||||
|
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
|
||||||
|
-->
|
||||||
|
|
||||||
|
<project name="privateBuildDeveloper" default="sleighCompile">
|
||||||
|
|
||||||
|
<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
|
||||||
|
|
||||||
|
<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
|
||||||
|
<import file="../.antProperties.xml" optional="false" />
|
||||||
|
|
||||||
|
<target name="sleighCompile">
|
||||||
|
|
||||||
|
<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
|
||||||
|
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>
|
||||||
|
|
||||||
|
<path id="sleigh.class.path">
|
||||||
|
<fileset dir="${framework.path}/SoftwareModeling/lib">
|
||||||
|
<include name="*.jar"/>
|
||||||
|
</fileset>
|
||||||
|
<fileset dir="${framework.path}/Generic/lib">
|
||||||
|
<include name="*.jar"/>
|
||||||
|
</fileset>
|
||||||
|
<fileset dir="${framework.path}/Utility/lib">
|
||||||
|
<include name="*.jar"/>
|
||||||
|
</fileset>
|
||||||
|
</path>
|
||||||
|
|
||||||
|
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
|
||||||
|
|
||||||
|
<fail unless="sleigh.compile.exists" />
|
||||||
|
|
||||||
|
<java classname="${sleigh.compile.class}"
|
||||||
|
classpathref="sleigh.class.path"
|
||||||
|
fork="true"
|
||||||
|
failonerror="true">
|
||||||
|
<jvmarg value="-Xmx2048M"/>
|
||||||
|
<arg value="-i"/>
|
||||||
|
<arg value="sleighArgs.txt"/>
|
||||||
|
<arg value="-a"/>
|
||||||
|
<arg value="./languages"/>
|
||||||
|
</java>
|
||||||
|
|
||||||
|
</target>
|
||||||
|
|
||||||
|
</project>
|
||||||
@ -1,6 +1,6 @@
|
|||||||
<opinions>
|
<opinions>
|
||||||
<constraint loader="Wii U / CafeOS Binary (RPX/RPL)" compilerSpecID="default">
|
<constraint loader="Wii U / CafeOS Binary (RPX/RPL)" compilerSpecID="default">
|
||||||
<constraint primary="wiiu" processor="PowerPC" endian="big" size="32" variant="Gekko/Broadway" />
|
<constraint primary="wiiu" processor="PowerPC" endian="big" size="32" variant="Gekko/Broadway/Espresso" />
|
||||||
<constraint primary="wiiu" processor="PowerPC" endian="big" size="32" variant="default" />
|
<constraint primary="wiiu" processor="PowerPC" endian="big" size="32" variant="default" />
|
||||||
</constraint>
|
</constraint>
|
||||||
</opinions>
|
</opinions>
|
||||||
|
|||||||
101
data/languages/lmwInstructions.sinc
Normal file
101
data/languages/lmwInstructions.sinc
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
LDMR0: is lsmul=1 {}
|
||||||
|
LDMR0: is epsilon { loadReg(r0); }
|
||||||
|
|
||||||
|
LDMR1: is lsmul=2 {}
|
||||||
|
LDMR1: is LDMR0 { build LDMR0; loadReg(r1); }
|
||||||
|
|
||||||
|
LDMR2: is lsmul=3 {}
|
||||||
|
LDMR2: is LDMR1 { build LDMR1; loadReg(r2); }
|
||||||
|
|
||||||
|
LDMR3: is lsmul=4 {}
|
||||||
|
LDMR3: is LDMR2 { build LDMR2; loadReg(r3); }
|
||||||
|
|
||||||
|
LDMR4: is lsmul=5 {}
|
||||||
|
LDMR4: is LDMR3 { build LDMR3; loadReg(r4); }
|
||||||
|
|
||||||
|
LDMR5: is lsmul=6 {}
|
||||||
|
LDMR5: is LDMR4 { build LDMR4; loadReg(r5); }
|
||||||
|
|
||||||
|
LDMR6: is lsmul=7 {}
|
||||||
|
LDMR6: is LDMR5 { build LDMR5; loadReg(r6); }
|
||||||
|
|
||||||
|
LDMR7: is lsmul=8 {}
|
||||||
|
LDMR7: is LDMR6 { build LDMR6; loadReg(r7); }
|
||||||
|
|
||||||
|
LDMR8: is lsmul=9 {}
|
||||||
|
LDMR8: is LDMR7 { build LDMR7; loadReg(r8); }
|
||||||
|
|
||||||
|
LDMR9: is lsmul=10 {}
|
||||||
|
LDMR9: is LDMR8 { build LDMR8; loadReg(r9); }
|
||||||
|
|
||||||
|
LDMR10: is lsmul=11 {}
|
||||||
|
LDMR10: is LDMR9 { build LDMR9; loadReg(r10); }
|
||||||
|
|
||||||
|
LDMR11: is lsmul=12 {}
|
||||||
|
LDMR11: is LDMR10 { build LDMR10; loadReg(r11); }
|
||||||
|
|
||||||
|
LDMR12: is lsmul=13 {}
|
||||||
|
LDMR12: is LDMR11 { build LDMR11; loadReg(r12); }
|
||||||
|
|
||||||
|
LDMR13: is lsmul=14 {}
|
||||||
|
LDMR13: is LDMR12 { build LDMR12; loadReg(r13); }
|
||||||
|
|
||||||
|
LDMR14: is lsmul=15 {}
|
||||||
|
LDMR14: is LDMR13 { build LDMR13; loadReg(r14); }
|
||||||
|
|
||||||
|
LDMR15: is lsmul=16 {}
|
||||||
|
LDMR15: is LDMR14 { build LDMR14; loadReg(r15); }
|
||||||
|
|
||||||
|
LDMR16: is lsmul=17 {}
|
||||||
|
LDMR16: is LDMR15 { build LDMR15; loadReg(r16); }
|
||||||
|
|
||||||
|
LDMR17: is lsmul=18 {}
|
||||||
|
LDMR17: is LDMR16 { build LDMR16; loadReg(r17); }
|
||||||
|
|
||||||
|
LDMR18: is lsmul=19 {}
|
||||||
|
LDMR18: is LDMR17 { build LDMR17; loadReg(r18); }
|
||||||
|
|
||||||
|
LDMR19: is lsmul=20 {}
|
||||||
|
LDMR19: is LDMR18 { build LDMR18; loadReg(r19); }
|
||||||
|
|
||||||
|
LDMR20: is lsmul=21 {}
|
||||||
|
LDMR20: is LDMR19 { build LDMR19; loadReg(r20); }
|
||||||
|
|
||||||
|
LDMR21: is lsmul=22 {}
|
||||||
|
LDMR21: is LDMR20 { build LDMR20; loadReg(r21); }
|
||||||
|
|
||||||
|
LDMR22: is lsmul=23 {}
|
||||||
|
LDMR22: is LDMR21 { build LDMR21; loadReg(r22); }
|
||||||
|
|
||||||
|
LDMR23: is lsmul=24 {}
|
||||||
|
LDMR23: is LDMR22 { build LDMR22; loadReg(r23); }
|
||||||
|
|
||||||
|
LDMR24: is lsmul=25 {}
|
||||||
|
LDMR24: is LDMR23 { build LDMR23; loadReg(r24); }
|
||||||
|
|
||||||
|
LDMR25: is lsmul=26 {}
|
||||||
|
LDMR25: is LDMR24 { build LDMR24; loadReg(r25); }
|
||||||
|
|
||||||
|
LDMR26: is lsmul=27 {}
|
||||||
|
LDMR26: is LDMR25 { build LDMR25; loadReg(r26); }
|
||||||
|
|
||||||
|
LDMR27: is lsmul=28 {}
|
||||||
|
LDMR27: is LDMR26 { build LDMR26; loadReg(r27); }
|
||||||
|
|
||||||
|
LDMR28: is lsmul=29 {}
|
||||||
|
LDMR28: is LDMR27 { build LDMR27; loadReg(r28); }
|
||||||
|
|
||||||
|
LDMR29: is lsmul=30 {}
|
||||||
|
LDMR29: is LDMR28 { build LDMR28; loadReg(r29); }
|
||||||
|
|
||||||
|
LDMR30: is lsmul=31 {}
|
||||||
|
LDMR30: is LDMR29 { build LDMR29; loadReg(r30); }
|
||||||
|
|
||||||
|
LDMR31: is LDMR30 { build LDMR30; loadReg(r31); }
|
||||||
|
|
||||||
|
:lmw D,dPlusRaOrZeroAddress is $(NOTVLE) & OP=46 & D & BITS_21_25 & dPlusRaOrZeroAddress & LDMR31 [ lsmul = BITS_21_25; ]
|
||||||
|
{
|
||||||
|
tea = dPlusRaOrZeroAddress;
|
||||||
|
build LDMR31;
|
||||||
|
}
|
||||||
|
|
||||||
185
data/languages/lswInstructions.sinc
Normal file
185
data/languages/lswInstructions.sinc
Normal file
@ -0,0 +1,185 @@
|
|||||||
|
#lswi r0,0,7 0x7c 00 3c aa
|
||||||
|
#lswi r0,r2,7 0x7c 02 3c aa
|
||||||
|
|
||||||
|
DYN_D1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_D7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
loadRegister(DYN_D5,ea);
|
||||||
|
loadRegister(DYN_D6,ea);
|
||||||
|
loadRegister(DYN_D7,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(D,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D1,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D2,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D3,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D4,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D5,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
loadRegister(DYN_D5,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
loadRegister(DYN_D5,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D6,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
loadRegister(DYN_D5,ea);
|
||||||
|
loadRegister(DYN_D6,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:lswi D,RA_OR_ZERO,NB is OP=31 & D & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=597 & BIT_0=0
|
||||||
|
& DYN_D1 & DYN_D2 & DYN_D3 & DYN_D4 & DYN_D5 & DYN_D6 & DYN_D7
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
loadRegister(D,ea);
|
||||||
|
loadRegister(DYN_D1,ea);
|
||||||
|
loadRegister(DYN_D2,ea);
|
||||||
|
loadRegister(DYN_D3,ea);
|
||||||
|
loadRegister(DYN_D4,ea);
|
||||||
|
loadRegister(DYN_D5,ea);
|
||||||
|
loadRegister(DYN_D6,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
loadRegisterPartial(DYN_D7,ea,sa);
|
||||||
|
}
|
||||||
219
data/languages/ppc_embedded.sinc
Normal file
219
data/languages/ppc_embedded.sinc
Normal file
@ -0,0 +1,219 @@
|
|||||||
|
# these are identified as part of the PowerPC Embedded Architecture
|
||||||
|
|
||||||
|
#dcba 0,r0 0x7c 00 05 ec
|
||||||
|
:dcba RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=758 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockAllocate(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbf 0,r0 0x7c 00 00 ac
|
||||||
|
:dcbf RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=86 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockFlush(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbi 0,r0 0x7c 00 03 ac
|
||||||
|
:dcbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=470 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockInvalidate(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbst 0,r0 0x7c 00 00 6c
|
||||||
|
:dcbst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=54 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockStore(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbt 0,r0 0x7c 00 02 2c
|
||||||
|
:dcbt RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=278 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockTouch(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbtst 0,r0 0x7c 00 01 ec
|
||||||
|
:dcbtst RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=246 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockTouchForStore(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#dcbz 0,r0 0x7c 00 07 ec
|
||||||
|
:dcbz RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
dataCacheBlockClearToZero(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
@ifndef IS_ISA
|
||||||
|
# this is equilent to "mbar 0"
|
||||||
|
#eieio 0x7c 00 06 ac
|
||||||
|
:eieio is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=854 & BIT_0=0
|
||||||
|
{
|
||||||
|
enforceInOrderExecutionIO();
|
||||||
|
}
|
||||||
|
@endif
|
||||||
|
|
||||||
|
#icbi r0,r0 0x7c 00 07 ac
|
||||||
|
:icbi RA_OR_ZERO,B is OP=31 & BITS_21_25=0 & B & XOP_1_10=982 & BIT_0=0 & RA_OR_ZERO
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
instructionCacheBlockInvalidate(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#icbt 0,r0 0x7c 00 02 0c
|
||||||
|
:icbt BITS_21_24,RA_OR_ZERO,B is OP=31 & BIT_25=0 & BITS_21_24 & RA_OR_ZERO & B & XOP_1_10=22 & BIT_0=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
instructionCacheBlockTouch(ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#isync 0x4c 00 01 2c
|
||||||
|
:isync is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=150 & BIT_0=0
|
||||||
|
{
|
||||||
|
instructionSynchronize();
|
||||||
|
}
|
||||||
|
|
||||||
|
#mfdcr r0,DCRN 0x7c 00 02 86
|
||||||
|
:mfdcr D, DCRN is OP=31 & D & DCRN & XOP_1_10=323 & BIT_0=0
|
||||||
|
{
|
||||||
|
D = DCRN;
|
||||||
|
}
|
||||||
|
|
||||||
|
#mfmsr r0 0x7c 00 00 a6
|
||||||
|
:mfmsr D is OP=31 & D & BITS_11_20=0 & XOP_1_10=83 & BIT_0=0
|
||||||
|
{
|
||||||
|
D = MSR;
|
||||||
|
}
|
||||||
|
|
||||||
|
#mfspr r0 0x7c 00 02 a6
|
||||||
|
:mfspr D,SPRVAL is OP=31 & D & SPRVAL & XOP_1_10=339 & BIT_0=0
|
||||||
|
{
|
||||||
|
D = SPRVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
#mftb r0,TBLr 0x7c 0c 42 e6
|
||||||
|
:mftb D,TBLr is $(NOTVLE) & OP=31 & D & TBR=392 & TBLr & XOP_1_10=371 & BIT_0=0
|
||||||
|
{
|
||||||
|
D = TBLr;
|
||||||
|
}
|
||||||
|
#mftb r0,TBUr 0x7c 0d 42 e6
|
||||||
|
:mftb D,TBUr is $(NOTVLE) & OP=31 & D & TBR=424 & TBUr & XOP_1_10=371 & BIT_0=0
|
||||||
|
{
|
||||||
|
D = TBUr;
|
||||||
|
}
|
||||||
|
|
||||||
|
#mtdcr DCRN,r0 0x7c 00 03 86
|
||||||
|
:mtdcr DCRN, D is OP=31 & D & DCRN & XOP_1_10=451 & BIT_0=0
|
||||||
|
{
|
||||||
|
DCRN = D;
|
||||||
|
}
|
||||||
|
|
||||||
|
#mtmsr r0,0 0x7c 00 01 24
|
||||||
|
:mtmsr S,0 is OP=31 & S & BITS_17_20=0 & MSR_L=0 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
|
||||||
|
{
|
||||||
|
bit58:$(REGISTER_SIZE) = (S >> 5) & 1; #bit 58
|
||||||
|
bit49:$(REGISTER_SIZE) = (S >> 14)& 1; #bit 49
|
||||||
|
bit59:$(REGISTER_SIZE) = (S >> 4) & 1; #bit 59
|
||||||
|
@ifdef BIT_64
|
||||||
|
tmp:8 = S & 0x00000000ffff6fcf; #0b00000000000000000000000000000000 1111 1111 1111 1111 0110 1111 1100 1111
|
||||||
|
tmp = tmp & ((bit58 | bit49) << 5);
|
||||||
|
tmp = tmp & ((bit59 | bit49) << 4);
|
||||||
|
MSR = MSR & 0xffffffff00009030 | tmp;
|
||||||
|
@else
|
||||||
|
tmp:4 = S & 0xffff6fcf;
|
||||||
|
tmp = tmp & ((bit58 | bit49) << 5);
|
||||||
|
tmp = tmp & ((bit59 | bit49) << 4);
|
||||||
|
MSR = MSR & 0x00009000 | tmp;
|
||||||
|
@endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#mtmsr r0,1 0x7c 01 01 24
|
||||||
|
:mtmsr S,1 is OP=31 & S & BITS_17_20=0 & MSR_L=1 & BITS_11_15=0 & XOP_1_10=146 & BIT_0=0
|
||||||
|
{
|
||||||
|
@ifdef BIT_64
|
||||||
|
mask:8 = 0x000000000000fffe;
|
||||||
|
@else
|
||||||
|
mask:4 = 0x0000fffe;
|
||||||
|
@endif
|
||||||
|
MSR = (MSR & ~mask) | (S & mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
#mtspr spr000,r0 0x7c 00 02 a6
|
||||||
|
:mtspr SPRVAL,S is OP=31 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
|
||||||
|
{
|
||||||
|
SPRVAL = S;
|
||||||
|
}
|
||||||
|
|
||||||
|
:mtspr SPRVAL,S is OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
|
||||||
|
[ linkreg=1; globalset(inst_next,linkreg); ]
|
||||||
|
{
|
||||||
|
SPRVAL = S;
|
||||||
|
}
|
||||||
|
|
||||||
|
:mtspr SPRVAL,S is linkreg=1 & OP=31 & BITS_11_20=0x100 & BITS_21_25=0 & SPRVAL & S & XOP_1_10=467 & BIT_0=0
|
||||||
|
[ linkreg=0; globalset(inst_start,linkreg); ]
|
||||||
|
{
|
||||||
|
SPRVAL = S;
|
||||||
|
}
|
||||||
|
|
||||||
|
:rfci is $(NOTVLE) & OP=19 & BITS_21_25=0 & BITS_16_20=0 & BITS_11_15=0 & XOP_1_10=51 & BIT_0=0
|
||||||
|
{
|
||||||
|
MSR = returnFromCriticalInterrupt(MSR, CSRR1);
|
||||||
|
local ra = CSRR0;
|
||||||
|
return[ra];
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
#rfi 0x4c 00 00 64
|
||||||
|
:rfi is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=50 & BIT_0=0
|
||||||
|
{
|
||||||
|
MSR = returnFromInterrupt(MSR, SRR1);
|
||||||
|
local ra = SRR0;
|
||||||
|
return[ra];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#tlbre 0x7c 00 07 64
|
||||||
|
:tlbre is OP=31 & XOP_1_10=946
|
||||||
|
{
|
||||||
|
TLBRead();
|
||||||
|
}
|
||||||
|
|
||||||
|
#tlbsx r0,r0,r0 0x7c 00 07 24
|
||||||
|
:tlbsx D,RA_OR_ZERO,B is OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
D = TLBSearchIndexed(D,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
#tlbsx. r0,r0,r0 0x7c 00 07 25
|
||||||
|
:tlbsx. D,RA_OR_ZERO,B is $(NOTVLE) & OP=31 & D & B & XOP_1_10=914 & RA_OR_ZERO & Rc=1
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
|
||||||
|
D = TLBSearchIndexed(D,ea);
|
||||||
|
cr0flags(D);
|
||||||
|
}
|
||||||
|
|
||||||
|
#tlbwe 0x7c 00 07 a4
|
||||||
|
:tlbwe D,A,B_BITS is OP=31 & D & A & B_BITS & XOP_1_10=978
|
||||||
|
{
|
||||||
|
D = TLBWrite(D,A,B_BITS:1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#wrtee r0 0x7c 00 01 06
|
||||||
|
:wrtee S is OP=31 & S & XOP_1_10=131
|
||||||
|
{
|
||||||
|
WriteExternalEnable(S);
|
||||||
|
}
|
||||||
|
|
||||||
|
#wrteei 0 0x7c 00 01 46
|
||||||
|
:wrteei BIT_15 is OP=31 & BIT_15 & XOP_1_10=163
|
||||||
|
{
|
||||||
|
WriteExternalEnableImmediate(BIT_15:1);
|
||||||
|
}
|
||||||
117
data/languages/ppc_gekko_broadway.cspec
Normal file
117
data/languages/ppc_gekko_broadway.cspec
Normal file
@ -0,0 +1,117 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
|
||||||
|
<compiler_spec>
|
||||||
|
<global>
|
||||||
|
<range space="ram"/>
|
||||||
|
</global>
|
||||||
|
<stackpointer register="r1" space="ram"/>
|
||||||
|
<default_proto>
|
||||||
|
<prototype name="__stdcall" extrapop="0" stackshift="0">
|
||||||
|
<input pointermax="8">
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f1"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f2"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f3"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f4"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f5"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f6"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f7"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="4" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f8"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r3"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r4"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r5"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r6"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r7"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r8"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r9"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4">
|
||||||
|
<register name="r10"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="500" align="4">
|
||||||
|
<addr offset="8" space="stack"/>
|
||||||
|
</pentry>
|
||||||
|
</input>
|
||||||
|
<output>
|
||||||
|
<pentry minsize="1" maxsize="8" metatype="float" extension="float">
|
||||||
|
<register name="f1"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="1" maxsize="4" extension="inttype">
|
||||||
|
<register name="r3"/>
|
||||||
|
</pentry>
|
||||||
|
<pentry minsize="5" maxsize="8">
|
||||||
|
<addr space="join" piece1="r3" piece2="r4"/>
|
||||||
|
</pentry>
|
||||||
|
</output>
|
||||||
|
<unaffected>
|
||||||
|
<register name="r2"/>
|
||||||
|
<register name="r13"/>
|
||||||
|
<register name="r14"/>
|
||||||
|
<register name="r15"/>
|
||||||
|
<register name="r16"/>
|
||||||
|
<register name="r17"/>
|
||||||
|
<register name="r18"/>
|
||||||
|
<register name="r19"/>
|
||||||
|
<register name="r20"/>
|
||||||
|
<register name="r21"/>
|
||||||
|
<register name="r22"/>
|
||||||
|
<register name="r23"/>
|
||||||
|
<register name="r24"/>
|
||||||
|
<register name="r25"/>
|
||||||
|
<register name="r26"/>
|
||||||
|
<register name="r27"/>
|
||||||
|
<register name="r28"/>
|
||||||
|
<register name="r29"/>
|
||||||
|
<register name="r30"/>
|
||||||
|
<register name="r31"/>
|
||||||
|
<register name="r1"/>
|
||||||
|
<register name="cr4"/>
|
||||||
|
<register name="GQR0"/>
|
||||||
|
<register name="GQR1"/>
|
||||||
|
<register name="GQR2"/>
|
||||||
|
<register name="GQR3"/>
|
||||||
|
<register name="GQR4"/>
|
||||||
|
<register name="GQR5"/>
|
||||||
|
<register name="GQR6"/>
|
||||||
|
<register name="GQR7"/>
|
||||||
|
</unaffected>
|
||||||
|
</prototype>
|
||||||
|
</default_proto>
|
||||||
|
|
||||||
|
<callfixup name="get_pc_thunk_lr">
|
||||||
|
<pcode>
|
||||||
|
<body><![CDATA[
|
||||||
|
LR = inst_dest + 4;
|
||||||
|
]]></body>
|
||||||
|
</pcode>
|
||||||
|
</callfixup>
|
||||||
|
|
||||||
|
</compiler_spec>
|
||||||
19
data/languages/ppc_gekko_broadway.ldefs
Normal file
19
data/languages/ppc_gekko_broadway.ldefs
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
|
||||||
|
<language_definitions>
|
||||||
|
<language processor="PowerPC"
|
||||||
|
endian="big"
|
||||||
|
size="32"
|
||||||
|
variant="Gekko/Broadway/Espresso"
|
||||||
|
version="1.5"
|
||||||
|
slafile="ppc_gekko_broadway.sla"
|
||||||
|
processorspec="ppc_gekko_broadway.pspec"
|
||||||
|
manualindexfile="../manuals/PowerPC.idx"
|
||||||
|
id="PowerPC:BE:32:Gekko_Broadway_Espresso">
|
||||||
|
<description>PowerPC 32-bit big endian (Gekko/Broadway/Espresso variant)</description>
|
||||||
|
<compiler name="default" spec="ppc_gekko_broadway.cspec" id="default"/>
|
||||||
|
<external_name tool="gnu" name="powerpc:common"/>
|
||||||
|
<external_name tool="IDA-PRO" name="ppc"/>
|
||||||
|
<external_name tool="DWARF.register.mapping.file" name="ppc.dwarf"/>
|
||||||
|
</language>
|
||||||
|
</language_definitions>
|
||||||
1156
data/languages/ppc_gekko_broadway.pspec
Normal file
1156
data/languages/ppc_gekko_broadway.pspec
Normal file
File diff suppressed because it is too large
Load Diff
1824
data/languages/ppc_gekko_broadway.slaspec
Normal file
1824
data/languages/ppc_gekko_broadway.slaspec
Normal file
File diff suppressed because it is too large
Load Diff
3815
data/languages/ppc_instructions_gekko_broadway.sinc
Normal file
3815
data/languages/ppc_instructions_gekko_broadway.sinc
Normal file
File diff suppressed because it is too large
Load Diff
101
data/languages/stmwInstructions.sinc
Normal file
101
data/languages/stmwInstructions.sinc
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
STMR0: is lsmul=1 {}
|
||||||
|
STMR0: is epsilon { storeReg(r0); }
|
||||||
|
|
||||||
|
STMR1: is lsmul=2 {}
|
||||||
|
STMR1: is STMR0 { build STMR0; storeReg(r1); }
|
||||||
|
|
||||||
|
STMR2: is lsmul=3 {}
|
||||||
|
STMR2: is STMR1 { build STMR1; storeReg(r2); }
|
||||||
|
|
||||||
|
STMR3: is lsmul=4 {}
|
||||||
|
STMR3: is STMR2 { build STMR2; storeReg(r3); }
|
||||||
|
|
||||||
|
STMR4: is lsmul=5 {}
|
||||||
|
STMR4: is STMR3 { build STMR3; storeReg(r4); }
|
||||||
|
|
||||||
|
STMR5: is lsmul=6 {}
|
||||||
|
STMR5: is STMR4 { build STMR4; storeReg(r5); }
|
||||||
|
|
||||||
|
STMR6: is lsmul=7 {}
|
||||||
|
STMR6: is STMR5 { build STMR5; storeReg(r6); }
|
||||||
|
|
||||||
|
STMR7: is lsmul=8 {}
|
||||||
|
STMR7: is STMR6 { build STMR6; storeReg(r7); }
|
||||||
|
|
||||||
|
STMR8: is lsmul=9 {}
|
||||||
|
STMR8: is STMR7 { build STMR7; storeReg(r8); }
|
||||||
|
|
||||||
|
STMR9: is lsmul=10 {}
|
||||||
|
STMR9: is STMR8 { build STMR8; storeReg(r9); }
|
||||||
|
|
||||||
|
STMR10: is lsmul=11 {}
|
||||||
|
STMR10: is STMR9 { build STMR9; storeReg(r10); }
|
||||||
|
|
||||||
|
STMR11: is lsmul=12 {}
|
||||||
|
STMR11: is STMR10 { build STMR10; storeReg(r11); }
|
||||||
|
|
||||||
|
STMR12: is lsmul=13 {}
|
||||||
|
STMR12: is STMR11 { build STMR11; storeReg(r12); }
|
||||||
|
|
||||||
|
STMR13: is lsmul=14 {}
|
||||||
|
STMR13: is STMR12 { build STMR12; storeReg(r13); }
|
||||||
|
|
||||||
|
STMR14: is lsmul=15 {}
|
||||||
|
STMR14: is STMR13 { build STMR13; storeReg(r14); }
|
||||||
|
|
||||||
|
STMR15: is lsmul=16 {}
|
||||||
|
STMR15: is STMR14 { build STMR14; storeReg(r15); }
|
||||||
|
|
||||||
|
STMR16: is lsmul=17 {}
|
||||||
|
STMR16: is STMR15 { build STMR15; storeReg(r16); }
|
||||||
|
|
||||||
|
STMR17: is lsmul=18 {}
|
||||||
|
STMR17: is STMR16 { build STMR16; storeReg(r17); }
|
||||||
|
|
||||||
|
STMR18: is lsmul=19 {}
|
||||||
|
STMR18: is STMR17 { build STMR17; storeReg(r18); }
|
||||||
|
|
||||||
|
STMR19: is lsmul=20 {}
|
||||||
|
STMR19: is STMR18 { build STMR18; storeReg(r19); }
|
||||||
|
|
||||||
|
STMR20: is lsmul=21 {}
|
||||||
|
STMR20: is STMR19 { build STMR19; storeReg(r20); }
|
||||||
|
|
||||||
|
STMR21: is lsmul=22 {}
|
||||||
|
STMR21: is STMR20 { build STMR20; storeReg(r21); }
|
||||||
|
|
||||||
|
STMR22: is lsmul=23 {}
|
||||||
|
STMR22: is STMR21 { build STMR21; storeReg(r22); }
|
||||||
|
|
||||||
|
STMR23: is lsmul=24 {}
|
||||||
|
STMR23: is STMR22 { build STMR22; storeReg(r23); }
|
||||||
|
|
||||||
|
STMR24: is lsmul=25 {}
|
||||||
|
STMR24: is STMR23 { build STMR23; storeReg(r24); }
|
||||||
|
|
||||||
|
STMR25: is lsmul=26 {}
|
||||||
|
STMR25: is STMR24 { build STMR24; storeReg(r25); }
|
||||||
|
|
||||||
|
STMR26: is lsmul=27 {}
|
||||||
|
STMR26: is STMR25 { build STMR25; storeReg(r26); }
|
||||||
|
|
||||||
|
STMR27: is lsmul=28 {}
|
||||||
|
STMR27: is STMR26 { build STMR26; storeReg(r27); }
|
||||||
|
|
||||||
|
STMR28: is lsmul=29 {}
|
||||||
|
STMR28: is STMR27 { build STMR27; storeReg(r28); }
|
||||||
|
|
||||||
|
STMR29: is lsmul=30 {}
|
||||||
|
STMR29: is STMR28 { build STMR28; storeReg(r29); }
|
||||||
|
|
||||||
|
STMR30: is lsmul=31 {}
|
||||||
|
STMR30: is STMR29 { build STMR29; storeReg(r30); }
|
||||||
|
|
||||||
|
STMR31: is STMR30 { build STMR30; storeReg(r31); }
|
||||||
|
|
||||||
|
:stmw S,dPlusRaOrZeroAddress is $(NOTVLE) & OP=47 & S & BITS_21_25 & dPlusRaOrZeroAddress & STMR31 [ lsmul = BITS_21_25; ]
|
||||||
|
{
|
||||||
|
tea = dPlusRaOrZeroAddress;
|
||||||
|
build STMR31;
|
||||||
|
}
|
||||||
|
|
||||||
186
data/languages/stswiInstructions.sinc
Normal file
186
data/languages/stswiInstructions.sinc
Normal file
@ -0,0 +1,186 @@
|
|||||||
|
#stswi r5,r3,0x02 7c a4 14 aa
|
||||||
|
#stswi r5,r4,0x08 7c a4 44 aa
|
||||||
|
|
||||||
|
|
||||||
|
DYN_S1: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 1)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S2: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 2)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S3: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 3)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S4: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 4)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S5: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 5)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S6: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 6)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
DYN_S7: regaddr is BITS_21_25 [ regaddr = ((BITS_21_25 + 7)&0x1f) * $(REGISTER_SIZE); ] { export *[register]:$(REGISTER_SIZE) regaddr; }
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
storeRegister(DYN_S5,ea);
|
||||||
|
storeRegister(DYN_S6,ea);
|
||||||
|
storeRegister(DYN_S7,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=0 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(S,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=1 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S1,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=2 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S2,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=3 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S3,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=4 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S4,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=5 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S5,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
storeRegister(DYN_S5,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=6 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
storeRegister(DYN_S5,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S6,ea,sa);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH=0 & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
storeRegister(DYN_S5,ea);
|
||||||
|
storeRegister(DYN_S6,ea);
|
||||||
|
}
|
||||||
|
|
||||||
|
:stswi S,RA_OR_ZERO,NB is OP=31 & S & RA_OR_ZERO & NB & BITS_13_15=7 & BH & XOP_1_10=725 & BIT_0=0
|
||||||
|
& DYN_S1 & DYN_S2 & DYN_S3 & DYN_S4 & DYN_S5 & DYN_S6 & DYN_S7
|
||||||
|
{
|
||||||
|
ea:$(REGISTER_SIZE) = RA_OR_ZERO;
|
||||||
|
storeRegister(S,ea);
|
||||||
|
storeRegister(DYN_S1,ea);
|
||||||
|
storeRegister(DYN_S2,ea);
|
||||||
|
storeRegister(DYN_S3,ea);
|
||||||
|
storeRegister(DYN_S4,ea);
|
||||||
|
storeRegister(DYN_S5,ea);
|
||||||
|
storeRegister(DYN_S6,ea);
|
||||||
|
sa:1 = BH;
|
||||||
|
storeRegisterPartial(DYN_S7,ea,sa);
|
||||||
|
}
|
||||||
37
ghidra_scripts/fix_primary_imports.java
Normal file
37
ghidra_scripts/fix_primary_imports.java
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
// Sets all imported references to primary
|
||||||
|
//@author GaryOderNichts
|
||||||
|
//@category wiiu
|
||||||
|
//@keybinding
|
||||||
|
//@menupath
|
||||||
|
//@toolbar
|
||||||
|
|
||||||
|
import ghidra.app.script.GhidraScript;
|
||||||
|
import ghidra.program.model.mem.*;
|
||||||
|
import ghidra.program.model.lang.*;
|
||||||
|
import ghidra.program.model.pcode.*;
|
||||||
|
import ghidra.program.model.util.*;
|
||||||
|
import ghidra.program.model.reloc.*;
|
||||||
|
import ghidra.program.model.data.*;
|
||||||
|
import ghidra.program.model.block.*;
|
||||||
|
import ghidra.program.model.symbol.*;
|
||||||
|
import ghidra.program.model.scalar.*;
|
||||||
|
import ghidra.program.model.listing.*;
|
||||||
|
import ghidra.program.model.address.*;
|
||||||
|
|
||||||
|
public class fix_primary_imports extends GhidraScript {
|
||||||
|
|
||||||
|
public void run() throws Exception {
|
||||||
|
ReferenceManager refManager = currentProgram.getReferenceManager();
|
||||||
|
ReferenceIterator it = refManager.getReferenceIterator(currentProgram.getMinAddress());
|
||||||
|
|
||||||
|
while (it.hasNext()) {
|
||||||
|
Reference ref = it.next();
|
||||||
|
|
||||||
|
if (ref.getSource() == SourceType.IMPORTED) {
|
||||||
|
println("Setting primary reference for " + ref.getFromAddress().toString());
|
||||||
|
refManager.setPrimary(ref, true);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user