Ryujinx/Ryujinx.Graphics/Memory/NvGpuVmm.cs

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Add a new JIT compiler for CPU code (#693) * Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
using ARMeilleure.Memory;
using Ryujinx.Graphics.Gal;
using System;
namespace Ryujinx.Graphics.Memory
{
public class NvGpuVmm : IMemory, IGalMemory
{
public const long AddrSize = 1L << 40;
private const int PtLvl0Bits = 14;
private const int PtLvl1Bits = 14;
private const int PtPageBits = 12;
private const int PtLvl0Size = 1 << PtLvl0Bits;
private const int PtLvl1Size = 1 << PtLvl1Bits;
public const int PageSize = 1 << PtPageBits;
private const int PtLvl0Mask = PtLvl0Size - 1;
private const int PtLvl1Mask = PtLvl1Size - 1;
public const int PageMask = PageSize - 1;
private const int PtLvl0Bit = PtPageBits + PtLvl1Bits;
private const int PtLvl1Bit = PtPageBits;
public MemoryManager Memory { get; private set; }
private NvGpuVmmCache _cache;
private const long PteUnmapped = -1;
private const long PteReserved = -2;
private long[][] _pageTable;
public NvGpuVmm(MemoryManager memory)
{
Memory = memory;
_cache = new NvGpuVmmCache(memory);
_pageTable = new long[PtLvl0Size][];
}
public long Map(long pa, long va, long size)
{
lock (_pageTable)
{
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(va + offset, pa + offset);
}
}
return va;
}
public long Map(long pa, long size)
{
lock (_pageTable)
{
long va = GetFreePosition(size);
if (va != -1)
{
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(va + offset, pa + offset);
}
}
return va;
}
}
public long MapLow(long pa, long size)
{
lock (_pageTable)
{
long va = GetFreePosition(size, 1, PageSize);
if (va != -1 && (ulong)va <= uint.MaxValue && (ulong)(va + size) <= uint.MaxValue)
{
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(va + offset, pa + offset);
}
}
else
{
va = -1;
}
return va;
}
}
public long ReserveFixed(long va, long size)
{
lock (_pageTable)
{
for (long offset = 0; offset < size; offset += PageSize)
{
if (IsPageInUse(va + offset))
{
return -1;
}
}
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(va + offset, PteReserved);
}
}
return va;
}
public long Reserve(long size, long align)
{
lock (_pageTable)
{
long position = GetFreePosition(size, align);
if (position != -1)
{
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(position + offset, PteReserved);
}
}
return position;
}
}
public void Free(long va, long size)
{
lock (_pageTable)
{
for (long offset = 0; offset < size; offset += PageSize)
{
SetPte(va + offset, PteUnmapped);
}
}
}
private long GetFreePosition(long size, long align = 1, long start = 1L << 32)
{
// Note: Address 0 is not considered valid by the driver,
// when 0 is returned it's considered a mapping error.
long position = start;
long freeSize = 0;
if (align < 1)
{
align = 1;
}
align = (align + PageMask) & ~PageMask;
while (position + freeSize < AddrSize)
{
if (!IsPageInUse(position + freeSize))
{
freeSize += PageSize;
if (freeSize >= size)
{
return position;
}
}
else
{
position += freeSize + PageSize;
freeSize = 0;
long remainder = position % align;
if (remainder != 0)
{
position = (position - remainder) + align;
}
}
}
return -1;
}
public long GetPhysicalAddress(long va)
{
long basePos = GetPte(va);
if (basePos < 0)
{
return -1;
}
return basePos + (va & PageMask);
}
public bool IsRegionFree(long va, long size)
{
for (long offset = 0; offset < size; offset += PageSize)
{
if (IsPageInUse(va + offset))
{
return false;
}
}
return true;
}
private bool IsPageInUse(long va)
{
if (va >> PtLvl0Bits + PtLvl1Bits + PtPageBits != 0)
{
return false;
}
long l0 = (va >> PtLvl0Bit) & PtLvl0Mask;
long l1 = (va >> PtLvl1Bit) & PtLvl1Mask;
if (_pageTable[l0] == null)
{
return false;
}
return _pageTable[l0][l1] != PteUnmapped;
}
private long GetPte(long position)
{
long l0 = (position >> PtLvl0Bit) & PtLvl0Mask;
long l1 = (position >> PtLvl1Bit) & PtLvl1Mask;
if (_pageTable[l0] == null)
{
return -1;
}
return _pageTable[l0][l1];
}
private void SetPte(long position, long tgtAddr)
{
long l0 = (position >> PtLvl0Bit) & PtLvl0Mask;
long l1 = (position >> PtLvl1Bit) & PtLvl1Mask;
if (_pageTable[l0] == null)
{
_pageTable[l0] = new long[PtLvl1Size];
for (int index = 0; index < PtLvl1Size; index++)
{
_pageTable[l0][index] = PteUnmapped;
}
}
_pageTable[l0][l1] = tgtAddr;
}
public bool IsRegionModified(long pa, long size, NvGpuBufferType bufferType)
{
return _cache.IsRegionModified(pa, size, bufferType);
}
public bool TryGetHostAddress(long position, long size, out IntPtr ptr)
{
return Memory.TryGetHostAddress(GetPhysicalAddress(position), size, out ptr);
}
public byte ReadByte(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadByte(position);
}
public ushort ReadUInt16(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadUInt16(position);
}
public uint ReadUInt32(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadUInt32(position);
}
public ulong ReadUInt64(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadUInt64(position);
}
public sbyte ReadSByte(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadSByte(position);
}
public short ReadInt16(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadInt16(position);
}
public int ReadInt32(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadInt32(position);
}
public long ReadInt64(long position)
{
position = GetPhysicalAddress(position);
return Memory.ReadInt64(position);
}
public byte[] ReadBytes(long position, long size)
{
position = GetPhysicalAddress(position);
return Memory.ReadBytes(position, size);
}
public void WriteByte(long position, byte value)
{
position = GetPhysicalAddress(position);
Memory.WriteByte(position, value);
}
public void WriteUInt16(long position, ushort value)
{
position = GetPhysicalAddress(position);
Memory.WriteUInt16(position, value);
}
public void WriteUInt32(long position, uint value)
{
position = GetPhysicalAddress(position);
Memory.WriteUInt32(position, value);
}
public void WriteUInt64(long position, ulong value)
{
position = GetPhysicalAddress(position);
Memory.WriteUInt64(position, value);
}
public void WriteSByte(long position, sbyte value)
{
position = GetPhysicalAddress(position);
Memory.WriteSByte(position, value);
}
public void WriteInt16(long position, short value)
{
position = GetPhysicalAddress(position);
Memory.WriteInt16(position, value);
}
public void WriteInt32(long position, int value)
{
position = GetPhysicalAddress(position);
Memory.WriteInt32(position, value);
}
public void WriteInt64(long position, long value)
{
position = GetPhysicalAddress(position);
Memory.WriteInt64(position, value);
}
public void WriteBytes(long position, byte[] data)
{
position = GetPhysicalAddress(position);
Memory.WriteBytes(position, data);
}
}
}