mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 13:43:17 +02:00
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
This commit is contained in:
parent
0e343a748d
commit
59d1b2ad83
@ -183,7 +183,7 @@ namespace ChocolArm64
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Set("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg));
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Set("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg));
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Set("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElem));
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Set("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF));
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Set("000111100x100000010000xxxxxxxxxx", AInstEmit.Fmov_S, typeof(AOpCodeSimd));
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Set("00011110xx1xxxxxxxx100xxxxxxxxxx", AInstEmit.Fmov_Si, typeof(AOpCodeSimdFmov));
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Set("0xx0111100000xxx111101xxxxxxxxxx", AInstEmit.Fmov_V, typeof(AOpCodeSimdImm));
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@ -194,7 +194,7 @@ namespace ChocolArm64
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Set("000111110x0xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fmsub_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx000010xxxxxxxxxx", AInstEmit.Fmul_S, typeof(AOpCodeSimdReg));
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Set("0>1011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmul_V, typeof(AOpCodeSimdReg));
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Set("0x0011111<<xxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Ve, typeof(AOpCodeSimdRegElem));
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Set("0x0011111<<xxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Ve, typeof(AOpCodeSimdRegElemF));
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Set("000111100x100001010000xxxxxxxxxx", AInstEmit.Fneg_S, typeof(AOpCodeSimdReg));
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Set("000111110x1xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fnmsub_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx100010xxxxxxxxxx", AInstEmit.Fnmul_S, typeof(AOpCodeSimdReg));
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@ -225,6 +225,7 @@ namespace ChocolArm64
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Set("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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Set("0xx0111100000xxx111001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
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Set("0x001110<<1xxxxx100111xxxxxxxxxx", AInstEmit.Mul_V, typeof(AOpCodeSimdReg));
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Set("0x001111xxxxxxxx1000x0xxxxxxxxxx", AInstEmit.Mul_Ve, typeof(AOpCodeSimdRegElem));
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Set("0x10111100000xxx0xx001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
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Set("0x10111100000xxx10x001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
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Set("0x10111100000xxx110x01xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm));
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@ -4,9 +4,9 @@ namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdReg : AOpCodeSimd
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{
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public bool Bit3 { get; private set; }
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public int Ra { get; private set; }
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public int Rm { get; private set; }
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public bool Bit3 { get; private set; }
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public int Ra { get; private set; }
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public int Rm { get; protected set; }
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public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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@ -8,15 +8,27 @@ namespace ChocolArm64.Decoder
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public AOpCodeSimdRegElem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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if ((Size & 1) != 0)
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switch (Size)
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{
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Index = (OpCode >> 11) & 1;
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}
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else
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{
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Index = (OpCode >> 21) & 1 |
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(OpCode >> 10) & 2;
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case 1:
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Index = (OpCode >> 21) & 1 |
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(OpCode >> 10) & 2 |
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(OpCode >> 18) & 4;
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Rm &= 0xf;
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break;
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case 2:
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Index = (OpCode >> 21) & 1 |
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(OpCode >> 10) & 2;
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break;
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default: Emitter = AInstEmit.Und; return;
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}
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}
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}
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}
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22
ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
Normal file
22
ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
Normal file
@ -0,0 +1,22 @@
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using ChocolArm64.Instruction;
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namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdRegElemF : AOpCodeSimdReg
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{
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public int Index { get; private set; }
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public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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if ((Size & 1) != 0)
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{
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Index = (OpCode >> 11) & 1;
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}
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else
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{
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Index = (OpCode >> 21) & 1 |
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(OpCode >> 10) & 2;
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}
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}
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}
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}
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@ -341,6 +341,11 @@ namespace ChocolArm64.Instruction
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Mul_Ve(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpByElemZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Neg_V(AILEmitterCtx Context)
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{
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EmitVectorUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
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@ -99,6 +99,11 @@ namespace ChocolArm64.Instruction
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EmitVectorInsertF(Context, Op.Rd, Part + Index, 0);
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}
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Fcvtps_Gp(AILEmitterCtx Context)
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@ -200,20 +200,6 @@ namespace ChocolArm64.Instruction
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EmitVectorOpF(Context, Emit, OperFlags.RdRnRm);
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}
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public static void EmitVectorBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: false);
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}
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public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: true);
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}
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public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -250,6 +236,20 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void EmitVectorBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
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EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: false);
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}
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public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
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EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: true);
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}
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public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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@ -341,6 +341,54 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void EmitVectorBinaryOpByElemSx(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpByElem(Context, Emit, Op.Index, false, true);
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}
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public static void EmitVectorBinaryOpByElemZx(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpByElem(Context, Emit, Op.Index, false, false);
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}
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public static void EmitVectorTernaryOpByElemZx(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
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EmitVectorOpByElem(Context, Emit, Op.Index, true, false);
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}
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public static void EmitVectorOpByElem(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary, bool Signed)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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if (Ternary)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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EmitVectorExtract(Context, Op.Rm, Index, Op.Size, Signed);
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Emit();
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void EmitVectorImmUnaryOp(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorImmOp(Context, Emit, false);
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10
Ryujinx.Core/OsHle/ErrorCode.cs
Normal file
10
Ryujinx.Core/OsHle/ErrorCode.cs
Normal file
@ -0,0 +1,10 @@
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namespace Ryujinx.Core.OsHle
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{
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static class ErrorCode
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{
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public static uint MakeError(ErrorModule Module, int Code)
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{
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return (uint)Module | ((uint)Code << 9);
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}
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}
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}
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@ -1,4 +1,4 @@
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namespace Ryujinx.Core.OsHle.IpcServices
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namespace Ryujinx.Core.OsHle
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{
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enum ErrorModule
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{
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11
Ryujinx.Core/OsHle/KernelErr.cs
Normal file
11
Ryujinx.Core/OsHle/KernelErr.cs
Normal file
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namespace Ryujinx.Core.OsHle
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{
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static class KernelErr
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{
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public const int InvalidMemRange = 110;
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public const int InvalidHandle = 114;
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public const int Timeout = 117;
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public const int InvalidInfo = 120;
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public const int InvalidIpcReq = 123;
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}
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}
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@ -1,10 +0,0 @@
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namespace Ryujinx.Core.OsHle.IpcServices
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{
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static class ErrorCode
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{
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public static long MakeError(ErrorModule Module, int Code)
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{
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return (int)Module | (Code << 9);
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}
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}
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}
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@ -4,7 +4,7 @@ using System.Collections.Generic;
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using System.IO;
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using System.Text;
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using static Ryujinx.Core.OsHle.IpcServices.ErrorCode;
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using static Ryujinx.Core.OsHle.ErrorCode;
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using static Ryujinx.Core.OsHle.IpcServices.ObjHelper;
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namespace Ryujinx.Core.OsHle.IpcServices.FspSrv
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@ -2,6 +2,8 @@ using ChocolArm64.Memory;
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using ChocolArm64.State;
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using Ryujinx.Core.OsHle.Handles;
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using static Ryujinx.Core.OsHle.ErrorCode;
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namespace Ryujinx.Core.OsHle.Svc
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{
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partial class SvcHandler
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@ -23,7 +25,7 @@ namespace Ryujinx.Core.OsHle.Svc
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CurrentHeapSize = Size;
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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ThreadState.X1 = (ulong)Position;
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}
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@ -44,7 +46,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Memory.Manager.SetAttrBit(Position, Size, 3);
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}
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcMapMemory(AThreadState ThreadState)
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@ -61,7 +63,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Memory.Manager.SetAttrBit(Src, Size, 0);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcUnmapMemory(AThreadState ThreadState)
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@ -78,7 +80,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Memory.Manager.ClearAttrBit(Src, Size, 0);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcQueryMemory(AThreadState ThreadState)
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@ -86,12 +88,13 @@ namespace Ryujinx.Core.OsHle.Svc
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long InfoPtr = (long)ThreadState.X0;
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long Position = (long)ThreadState.X2;
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Position &= uint.MaxValue;
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AMemoryMapInfo MapInfo = Memory.Manager.GetMapInfo(Position);
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if (MapInfo == null)
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{
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//TODO: Correct error code.
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ThreadState.X0 = ulong.MaxValue;
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ThreadState.X0 = MakeError(ErrorModule.Kernel, KernelErr.InvalidMemRange);
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return;
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}
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@ -106,7 +109,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Memory.WriteInt32(InfoPtr + 0x24, 0);
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//TODO: X1.
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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ThreadState.X1 = 0;
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}
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@ -127,7 +130,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Memory.Manager.Map(Src, Size, (int)MemoryType.SharedMemory, (AMemoryPerm)Perm);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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//TODO: Error codes.
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@ -143,7 +146,7 @@ namespace Ryujinx.Core.OsHle.Svc
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if (HndData != null)
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{
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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//TODO: Error codes.
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@ -164,7 +167,7 @@ namespace Ryujinx.Core.OsHle.Svc
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int Handle = Ns.Os.Handles.GenerateId(HndData);
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ThreadState.X1 = (ulong)Handle;
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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}
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}
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@ -1,11 +0,0 @@
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namespace Ryujinx.Core.OsHle.Svc
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{
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enum SvcResult
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{
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Success = 0,
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ErrBadHandle = 0xe401,
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ErrTimeout = 0xea01,
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ErrBadInfo = 0xf001,
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ErrBadIpcReq = 0xf601
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}
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}
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@ -7,6 +7,8 @@ using Ryujinx.Core.OsHle.IpcServices;
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using System;
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using System.Threading;
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using static Ryujinx.Core.OsHle.ErrorCode;
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namespace Ryujinx.Core.OsHle.Svc
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{
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partial class SvcHandler
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@ -26,7 +28,7 @@ namespace Ryujinx.Core.OsHle.Svc
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//TODO: Implement events.
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcCloseHandle(AThreadState ThreadState)
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@ -35,7 +37,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Ns.Os.CloseHandle(Handle);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcResetSignal(AThreadState ThreadState)
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@ -44,7 +46,7 @@ namespace Ryujinx.Core.OsHle.Svc
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//TODO: Implement events.
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcWaitSynchronization(AThreadState ThreadState)
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@ -60,7 +62,7 @@ namespace Ryujinx.Core.OsHle.Svc
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Process.Scheduler.Suspend(CurrThread.ProcessorId);
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Process.Scheduler.Resume(CurrThread);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcGetSystemTick(AThreadState ThreadState)
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@ -81,7 +83,7 @@ namespace Ryujinx.Core.OsHle.Svc
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HSession Session = new HSession(ServiceFactory.MakeService(Name));
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ThreadState.X1 = (ulong)Ns.Os.Handles.GenerateId(Session);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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private void SvcSendSyncRequest(AThreadState ThreadState)
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@ -127,11 +129,11 @@ namespace Ryujinx.Core.OsHle.Svc
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byte[] Response = AMemoryHelper.ReadBytes(Memory, CmdPtr, (int)Size);
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ThreadState.X0 = (int)SvcResult.Success;
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ThreadState.X0 = 0;
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}
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else
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{
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ThreadState.X0 = (int)SvcResult.ErrBadIpcReq;
|
||||
ThreadState.X0 = MakeError(ErrorModule.Kernel, KernelErr.InvalidIpcReq);
|
||||
}
|
||||
|
||||
Thread.Yield();
|
||||
@ -157,7 +159,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
Logging.Info($"SvcOutputDebugString: {Str}");
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
private void SvcGetInfo(AThreadState ThreadState)
|
||||
@ -171,7 +173,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
if (InfoType == 18 ||
|
||||
InfoType == 19)
|
||||
{
|
||||
ThreadState.X0 = (int)SvcResult.ErrBadInfo;
|
||||
ThreadState.X0 = MakeError(ErrorModule.Kernel, KernelErr.InvalidInfo);
|
||||
|
||||
return;
|
||||
}
|
||||
@ -233,7 +235,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
default: throw new NotImplementedException($"SvcGetInfo: {InfoType} {Handle} {InfoId}");
|
||||
}
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -28,7 +28,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
Priority,
|
||||
ProcessorId);
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
ThreadState.X1 = (ulong)Handle;
|
||||
}
|
||||
|
||||
@ -45,7 +45,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
{
|
||||
Process.Scheduler.StartThread(Thread);
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
//TODO: Error codes.
|
||||
@ -75,8 +75,8 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
if (Thread != null)
|
||||
{
|
||||
ThreadState.X0 = 0;
|
||||
ThreadState.X1 = (ulong)Thread.Priority;
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
}
|
||||
|
||||
//TODO: Error codes.
|
||||
@ -93,7 +93,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
{
|
||||
Thread.Priority = Prio;
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
//TODO: Error codes.
|
||||
@ -101,7 +101,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
private void SvcSetThreadCoreMask(AThreadState ThreadState)
|
||||
{
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
|
||||
//TODO: Error codes.
|
||||
}
|
||||
@ -114,8 +114,8 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
if (Thread != null)
|
||||
{
|
||||
ThreadState.X0 = 0;
|
||||
ThreadState.X1 = (ulong)Thread.ThreadId;
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
}
|
||||
|
||||
//TODO: Error codes.
|
||||
|
@ -1,6 +1,8 @@
|
||||
using ChocolArm64.State;
|
||||
using Ryujinx.Core.OsHle.Handles;
|
||||
|
||||
using static Ryujinx.Core.OsHle.ErrorCode;
|
||||
|
||||
namespace Ryujinx.Core.OsHle.Svc
|
||||
{
|
||||
partial class SvcHandler
|
||||
@ -19,7 +21,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
M.WaitForLock(RequestingThread, RequestingThreadHandle);
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
private void SvcArbitrateUnlock(AThreadState ThreadState)
|
||||
@ -31,7 +33,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
M.Unlock();
|
||||
}
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
private void SvcWaitProcessWideKeyAtomic(AThreadState ThreadState)
|
||||
@ -55,14 +57,14 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
|
||||
if (!Cv.WaitForSignal(Thread))
|
||||
{
|
||||
ThreadState.X0 = (int)SvcResult.ErrTimeout;
|
||||
ThreadState.X0 = MakeError(ErrorModule.Kernel, KernelErr.Timeout);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
M.WaitForLock(Thread, ThreadHandle);
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
|
||||
private void SvcSignalProcessWideKey(AThreadState ThreadState)
|
||||
@ -77,7 +79,7 @@ namespace Ryujinx.Core.OsHle.Svc
|
||||
Cv.SetSignal(CurrThread, Count);
|
||||
}
|
||||
|
||||
ThreadState.X0 = (int)SvcResult.Success;
|
||||
ThreadState.X0 = 0;
|
||||
}
|
||||
}
|
||||
}
|
Loading…
Reference in New Issue
Block a user