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Remove CpuId IR instruction (#1227)
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@ -53,7 +53,6 @@ namespace ARMeilleure.CodeGen.X86
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Add(Instruction.ConvertToFP, GenerateConvertToFP);
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Add(Instruction.Copy, GenerateCopy);
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Add(Instruction.CountLeadingZeros, GenerateCountLeadingZeros);
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Add(Instruction.CpuId, GenerateCpuId);
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Add(Instruction.Divide, GenerateDivide);
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Add(Instruction.DivideUI, GenerateDivideUI);
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Add(Instruction.Fill, GenerateFill);
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@ -765,11 +764,6 @@ namespace ARMeilleure.CodeGen.X86
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context.Assembler.Xor(dest, Const(operandMask), OperandType.I32);
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}
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private static void GenerateCpuId(CodeGenContext context, Operation operation)
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{
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context.Assembler.Cpuid();
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}
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private static void GenerateDivide(CodeGenContext context, Operation operation)
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{
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Operand dest = operation.Destination;
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@ -265,38 +265,6 @@ namespace ARMeilleure.CodeGen.X86
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break;
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}
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case Instruction.CpuId:
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{
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// Handle the many restrictions of the CPU Id instruction:
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// - EAX controls the information returned by this instruction.
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// - When EAX is 1, feature information is returned.
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// - The information is written to registers EAX, EBX, ECX and EDX.
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Debug.Assert(dest.Type == OperandType.I64);
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Operand eax = Gpr(X86Register.Rax, OperandType.I32);
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Operand ebx = Gpr(X86Register.Rbx, OperandType.I32);
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Operand ecx = Gpr(X86Register.Rcx, OperandType.I32);
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Operand edx = Gpr(X86Register.Rdx, OperandType.I32);
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// Value 0x01 = Version, family and feature information.
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nodes.AddBefore(node, Operation(Instruction.Copy, eax, Const(1)));
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// Copy results to the destination register.
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// The values are split into 2 32-bits registers, we merge them
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// into a single 64-bits register.
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Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
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node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, dest, edx));
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node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, dest, dest, Const(32)));
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node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, dest, dest, rcx));
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operation.SetDestinations(new Operand[] { eax, ebx, ecx, edx });
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operation.SetSources(new Operand[] { eax });
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break;
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}
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case Instruction.Divide:
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case Instruction.DivideUI:
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{
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@ -69,7 +69,6 @@ namespace ARMeilleure.IntermediateRepresentation
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ZeroExtend8,
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Clobber,
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CpuId,
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Extended,
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Fill,
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LoadFromContext,
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@ -209,11 +209,6 @@ namespace ARMeilleure.Translation
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return Add(Instruction.CountLeadingZeros, Local(op1.Type), op1);
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}
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internal Operand CpuId()
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{
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return Add(Instruction.CpuId, Local(OperandType.I64));
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}
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public Operand Divide(Operand op1, Operand op2)
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{
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return Add(Instruction.Divide, Local(op1.Type), op1, op2);
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