2021-08-01 15:32:48 +02:00
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module SummerCart64 (
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input i_clk,
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2021-08-12 21:07:47 +02:00
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output o_usb_clk,
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output o_usb_cs,
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input i_usb_miso,
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inout [3:0] io_usb_miosi,
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2021-08-18 13:54:07 +02:00
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input i_usb_pwren,
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2021-08-12 21:07:47 +02:00
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2021-08-16 00:23:10 +02:00
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input i_uart_rxd,
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output o_uart_txd,
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input i_uart_cts,
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output o_uart_rts,
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2021-08-01 15:32:48 +02:00
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input i_n64_reset,
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input i_n64_nmi,
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2021-08-12 21:07:47 +02:00
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output o_n64_irq,
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2021-08-01 15:32:48 +02:00
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input i_n64_pi_alel,
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input i_n64_pi_aleh,
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input i_n64_pi_read,
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input i_n64_pi_write,
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inout [15:0] io_n64_pi_ad,
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input i_n64_si_clk,
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inout io_n64_si_dq,
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output o_sdram_clk,
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output o_sdram_cs,
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output o_sdram_ras,
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output o_sdram_cas,
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output o_sdram_we,
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output [1:0] o_sdram_ba,
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output [12:0] o_sdram_a,
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inout [15:0] io_sdram_dq,
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output o_sd_clk,
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inout io_sd_cmd,
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inout [3:0] io_sd_dat,
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2021-08-05 19:50:29 +02:00
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inout io_rtc_scl,
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inout io_rtc_sda,
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2021-08-16 00:23:10 +02:00
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output o_led
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);
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2021-08-18 13:54:07 +02:00
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logic [7:0] gpio_o;
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logic [7:0] gpio_i;
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logic [7:0] gpio_oe;
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2021-08-01 15:32:48 +02:00
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2021-08-18 13:54:07 +02:00
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always_comb begin
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o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ;
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o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ;
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gpio_i = {4'b0000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
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end
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2021-08-12 21:07:47 +02:00
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2021-08-18 13:54:07 +02:00
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if_system sys (
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.in_clk(i_clk),
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.n64_reset(i_n64_reset),
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.n64_nmi(i_n64_nmi)
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);
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system system_inst (
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.sys(sys)
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);
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2021-08-01 15:32:48 +02:00
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2021-08-12 21:07:47 +02:00
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cpu_soc cpu_soc_inst (
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.sys(sys),
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2021-08-12 21:07:47 +02:00
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.gpio_o(gpio_o),
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.gpio_i(gpio_i),
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.gpio_oe(gpio_oe),
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2021-08-18 13:54:07 +02:00
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.i2c_scl(io_rtc_scl),
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.i2c_sda(io_rtc_sda),
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2021-08-12 21:07:47 +02:00
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.usb_clk(o_usb_clk),
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.usb_cs(o_usb_cs),
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.usb_miso(i_usb_miso),
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.usb_miosi(io_usb_miosi),
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2021-08-18 13:54:07 +02:00
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.usb_pwren(i_usb_pwren),
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.uart_rxd(i_uart_rxd),
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.uart_txd(o_uart_txd),
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.uart_cts(i_uart_cts),
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.uart_rts(o_uart_rts)
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);
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logic n64_request;
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logic n64_ack;
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logic n64_write;
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logic [31:0] n64_address;
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logic [15:0] n64_wdata;
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logic [15:0] n64_rdata;
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n64_pi n64_pi_inst (
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.sys(sys),
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.n64_pi_alel(i_n64_pi_alel),
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.n64_pi_aleh(i_n64_pi_aleh),
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.n64_pi_read(i_n64_pi_read),
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.n64_pi_write(i_n64_pi_write),
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.n64_pi_ad(io_n64_pi_ad),
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.request(n64_request),
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.ack(n64_ack),
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.write(n64_write),
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.address(n64_address),
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.wdata(n64_wdata),
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.rdata(n64_rdata)
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);
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logic flash_request;
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logic [31:0] flash_rdata;
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logic flash_busy;
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logic flash_ack;
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logic in_address;
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logic dummy_ack;
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intel_flash intel_flash_inst (
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.clock(sys.clk),
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.reset_n(~sys.reset),
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.avmm_data_addr(n64_address[31:2]),
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.avmm_data_read((n64_ack && in_address) || flash_request),
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.avmm_data_readdata(flash_rdata),
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.avmm_data_waitrequest(flash_busy),
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.avmm_data_readdatavalid(flash_ack),
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.avmm_data_burstcount(2'd1)
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);
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2021-08-01 15:32:48 +02:00
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2021-08-18 13:54:07 +02:00
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always_ff @(posedge sys.clk) begin
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dummy_ack <= 1'b0;
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if (sys.reset) begin
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flash_request <= 1'b0;
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end else begin
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if (!flash_busy) begin
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flash_request <= 1'b0;
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end
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if (n64_request && in_address) begin
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flash_request <= 1'b1;
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end
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if (!in_address && n64_request) begin
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dummy_ack <= 1'b1;
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end
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end
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end
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always_comb begin
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in_address = n64_address < 32'h10008000;
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n64_rdata = n64_address[1] ? {flash_rdata[23:16], flash_rdata[31:24]} : {flash_rdata[7:0], flash_rdata[15:8]};
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if (!in_address) n64_rdata = 32'd0;
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n64_ack = 1'b0;
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if (in_address) begin
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n64_ack = flash_ack;
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end else begin
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n64_ack = dummy_ack;
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end
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end
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2021-08-01 15:32:48 +02:00
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endmodule
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