SummerCart64/sw/bootloader/src/io.c

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[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19) * isv support + usb/dd improvements * make room for saves * update offset * fixed debug address * idk * exception * ironed out all broken stuff * cleanup * return epc fix * better * more cleanup * even more cleanup * mooore cleanup * fixed printf * no assert * improved docker build, pyft232 instead of pyserial * fixed displaying long message strings description test * just straight cleanup * smallest cleanup * PAL * cpu buffer * n64 bootloader done * super slow usb storage reading implemented * reduced buffer size * usb gets fast * little cleanup * double buffered reads * removed separate event id * ISV in hardware finally * small exception changes * mac testing * py spacing * fsd write, rtc, isv and reset fixes * fixxx * good stopping point * usb fixed? * pretend we have 128 MB sdram * backup * chmod * test * test done * more tests * user rm * help * final fix * updated component values * nice asset names * cic 64dd support * ddipl enable separation * pre DMA rewrite, created dedicated buffer memory space, simplified code * dma rewrite, needs testing * moved xml * dd basics * timing * 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite * added usb read functionality, general cleanup * changed mem addressing * added fpga flash update access * added mcu update * chmod * little cleanup * update format and stuff * fixes * uninitialized fix * small fixes * update fixes * update stuff done * fpga update tested * build time fix * boot fix * test timing * readme test * test 2 * reports * testseet * final * build test * forgot * button and naming * General cleanup And multiline commit message test * Exception screen UI touch ups * display separation and tests beginning * pc software update * pc software done * timing test * delete launch.json * sw fixes * fixed button hole diameter in shell * small cleanup, rpi testing * shell fillet fix, pc rtc printing * added cfg lock mechanism * moved lock to cfg address space * extended ROM and ISV fixes * preliminary sd card support * little sd card cleanup * sd menu fixes * 5 second limit * reduced shell thickness * basic led act blinking * faster sd menu loading * inst cache invalidate * sd card writing is working * SD card CSD and CID registers * wait for previous command * led error codes * fixed cfg_translate_address use * 64dd from sd card working * 64dd speedup and button handling * delayed address latching cycle - might break other builds, needs testing * bootloader improvements * small fixes * return previous cfg when setting new * cache stuff * unfloader debug protocol support * UNFLoader style debug command line support * requirements.txt * shell groove fillet * reset state inside controller * fixed fast PI read, added PI R/W fifo debug info * PI access prioritize * SD clock stop when RX FIFO is more than half full * flash erase method change * CFG error handling, TLOZ MM debug ISV support * CIC5167 support * general fixes * USB unplugged cable handling * turn off led when changing between error/act modes * rtc 2 bit clock stop support * line endings * Revert "line endings" This reverts commit d0ddfe5ec716d2db7c72561703f51a94bf34e6bb. * PI address debug * readme test * diagram update * diagram background * diagram background * diagram background * updated readme
2022-11-10 11:46:54 +01:00
#include "io.h"
#include "vr4300.h"
static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) {
uint32_t cache_address = (((uint32_t) (address)) & (~(line_size - 1)));
while (cache_address < ((uint32_t) (address) + length)) {
asm volatile (
"cache %[operation], (%[cache_address]) \n" ::
[operation] "i" (operation),
[cache_address] "r" (cache_address)
);
cache_address += line_size;
}
}
void cache_data_hit_writeback_invalidate (void *address, size_t length) {
cache_operation(HIT_WRITE_BACK_INVALIDATE_D, CACHE_LINE_SIZE_D, address, length);
}
void cache_data_hit_writeback (void *address, size_t length) {
cache_operation(HIT_WRITE_BACK_D, CACHE_LINE_SIZE_D, address, length);
}
void cache_inst_hit_invalidate (void *address, size_t length) {
cache_operation(HIT_INVALIDATE_I, CACHE_LINE_SIZE_I, address, length);
}
uint32_t io_read (io32_t *address) {
io32_t *uncached = UNCACHED(address);
uint32_t value = *uncached;
return value;
}
void io_write (io32_t *address, uint32_t value) {
io32_t *uncached = UNCACHED(address);
*uncached = value;
}
uint32_t pi_busy (void) {
return (io_read(&PI->SR) & (PI_SR_IO_BUSY | PI_SR_DMA_BUSY));
}
uint32_t pi_io_read (io32_t *address) {
return io_read(address);
}
void pi_io_write (io32_t *address, uint32_t value) {
io_write(address, value);
while (pi_busy());
}
void pi_dma_read (io32_t *address, void *buffer, size_t length) {
cache_data_hit_writeback_invalidate(buffer, length);
io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
io_write(&PI->WDMA, length - 1);
while (pi_busy());
}
void pi_dma_write (io32_t *address, void *buffer, size_t length) {
cache_data_hit_writeback(buffer, length);
io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
io_write(&PI->RDMA, length - 1);
while (pi_busy());
}
uint32_t si_busy (void) {
return (io_read(&SI->SR) & (SI_SR_IO_BUSY | SI_SR_DMA_BUSY));
}
uint32_t si_io_read (io32_t *address) {
return io_read(address);
}
void si_io_write (io32_t *address, uint32_t value) {
io_write(address, value);
while (si_busy());
}