mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-01-06 18:08:12 +01:00
ff69030643
* isv support + usb/dd improvements
* make room for saves
* update offset
* fixed debug address
* idk
* exception
* ironed out all broken stuff
* cleanup
* return epc fix
* better
* more cleanup
* even more cleanup
* mooore cleanup
* fixed printf
* no assert
* improved docker build, pyft232 instead of pyserial
* fixed displaying long message strings
description test
* just straight cleanup
* smallest cleanup
* PAL
* cpu buffer
* n64 bootloader done
* super slow usb storage reading implemented
* reduced buffer size
* usb gets fast
* little cleanup
* double buffered reads
* removed separate event id
* ISV in hardware finally
* small exception changes
* mac testing
* py spacing
* fsd write, rtc, isv and reset fixes
* fixxx
* good stopping point
* usb fixed?
* pretend we have 128 MB sdram
* backup
* chmod
* test
* test done
* more tests
* user rm
* help
* final fix
* updated component values
* nice asset names
* cic 64dd support
* ddipl enable separation
* pre DMA rewrite, created dedicated buffer memory space, simplified code
* dma rewrite, needs testing
* moved xml
* dd basics
* timing
* 64dd working yet again, isv brought back, dma fixes, usb path rewrite, pc code rewrite
* added usb read functionality, general cleanup
* changed mem addressing
* added fpga flash update access
* added mcu update
* chmod
* little cleanup
* update format and stuff
* fixes
* uninitialized fix
* small fixes
* update fixes
* update stuff done
* fpga update tested
* build time fix
* boot fix
* test timing
* readme test
* test 2
* reports
* testseet
* final
* build test
* forgot
* button and naming
* General cleanup
And multiline commit message test
* Exception screen UI touch ups
* display separation and tests beginning
* pc software update
* pc software done
* timing test
* delete launch.json
* sw fixes
* fixed button hole diameter in shell
* small cleanup, rpi testing
* shell fillet fix, pc rtc printing
* added cfg lock mechanism
* moved lock to cfg address space
* extended ROM and ISV fixes
* preliminary sd card support
* little sd card cleanup
* sd menu fixes
* 5 second limit
* reduced shell thickness
* basic led act blinking
* faster sd menu loading
* inst cache invalidate
* sd card writing is working
* SD card CSD and CID registers
* wait for previous command
* led error codes
* fixed cfg_translate_address use
* 64dd from sd card working
* 64dd speedup and button handling
* delayed address latching cycle - might break other builds, needs testing
* bootloader improvements
* small fixes
* return previous cfg when setting new
* cache stuff
* unfloader debug protocol support
* UNFLoader style debug command line support
* requirements.txt
* shell groove fillet
* reset state inside controller
* fixed fast PI read, added PI R/W fifo debug info
* PI access prioritize
* SD clock stop when RX FIFO is more than half full
* flash erase method change
* CFG error handling, TLOZ MM debug ISV support
* CIC5167 support
* general fixes
* USB unplugged cable handling
* turn off led when changing between error/act modes
* rtc 2 bit clock stop support
* line endings
* Revert "line endings"
This reverts commit d0ddfe5ec7
.
* PI address debug
* readme test
* diagram update
* diagram background
* diagram background
* diagram background
* updated readme
81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
#include "io.h"
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#include "vr4300.h"
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static void cache_operation (uint8_t operation, uint8_t line_size, void *address, size_t length) {
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uint32_t cache_address = (((uint32_t) (address)) & (~(line_size - 1)));
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while (cache_address < ((uint32_t) (address) + length)) {
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asm volatile (
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"cache %[operation], (%[cache_address]) \n" ::
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[operation] "i" (operation),
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[cache_address] "r" (cache_address)
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);
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cache_address += line_size;
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}
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}
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void cache_data_hit_writeback_invalidate (void *address, size_t length) {
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cache_operation(HIT_WRITE_BACK_INVALIDATE_D, CACHE_LINE_SIZE_D, address, length);
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}
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void cache_data_hit_writeback (void *address, size_t length) {
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cache_operation(HIT_WRITE_BACK_D, CACHE_LINE_SIZE_D, address, length);
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}
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void cache_inst_hit_invalidate (void *address, size_t length) {
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cache_operation(HIT_INVALIDATE_I, CACHE_LINE_SIZE_I, address, length);
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}
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uint32_t io_read (io32_t *address) {
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io32_t *uncached = UNCACHED(address);
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uint32_t value = *uncached;
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return value;
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}
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void io_write (io32_t *address, uint32_t value) {
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io32_t *uncached = UNCACHED(address);
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*uncached = value;
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}
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uint32_t pi_busy (void) {
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return (io_read(&PI->SR) & (PI_SR_IO_BUSY | PI_SR_DMA_BUSY));
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}
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uint32_t pi_io_read (io32_t *address) {
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return io_read(address);
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}
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void pi_io_write (io32_t *address, uint32_t value) {
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io_write(address, value);
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while (pi_busy());
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}
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void pi_dma_read (io32_t *address, void *buffer, size_t length) {
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cache_data_hit_writeback_invalidate(buffer, length);
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io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
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io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
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io_write(&PI->WDMA, length - 1);
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while (pi_busy());
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}
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void pi_dma_write (io32_t *address, void *buffer, size_t length) {
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cache_data_hit_writeback(buffer, length);
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io_write(&PI->PADDR, (uint32_t) (PHYSICAL(address)));
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io_write(&PI->MADDR, (uint32_t) (PHYSICAL(buffer)));
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io_write(&PI->RDMA, length - 1);
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while (pi_busy());
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}
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uint32_t si_busy (void) {
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return (io_read(&SI->SR) & (SI_SR_IO_BUSY | SI_SR_DMA_BUSY));
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}
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uint32_t si_io_read (io32_t *address) {
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return io_read(address);
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}
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void si_io_write (io32_t *address, uint32_t value) {
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io_write(address, value);
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while (si_busy());
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}
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