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reset vector update

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Polprzewodnikowy 2021-11-16 22:13:56 +01:00
parent 0ae6aed88f
commit 06aa5c9de2
2 changed files with 6 additions and 8 deletions
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2
fw/rtl/cpu/cpu_wrapper.sv
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@ -33,7 +33,7 @@ module cpu_wrapper (
.ENABLE_COUNTERS64(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0),
.PROGADDR_RESET({4'(sc64::ID_CPU_FLASH), 28'h003_5800})
.PROGADDR_RESET(sc64::CPU_RESET_VECTOR)
) cpu_inst (
.clk(sys.clk),
.resetn(~sys.reset),

12
fw/rtl/system/sc64.sv
View File

@ -30,12 +30,10 @@ package sc64;
__ID_DMA_END
} e_dma_id;
parameter bit [31:0] SC64_VER = 32'h53437632;
parameter int CLOCK_FREQUENCY = 32'd100_000_000;
parameter bit CPU_HAS_UART = 1'b0;
parameter int UART_BAUD_RATE = 32'd1_000_000;
parameter bit [31:0] SC64_VER = 32'h53437632;
parameter int CLOCK_FREQUENCY = 32'd100_000_000;
parameter bit [31:0] CPU_RESET_VECTOR = {4'(ID_CPU_FLASH), 28'h0035800};
parameter bit CPU_HAS_UART = 1'b0;
parameter int UART_BAUD_RATE = 32'd1_000_000;
endpackage