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Polprzewodnikowy 2021-08-18 13:54:07 +02:00
parent 8501b875f9
commit 0992680dd7
34 changed files with 1348 additions and 415 deletions
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3
fw/.gitignore vendored
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@ -7,3 +7,6 @@
*.rpt *.rpt
*.txt *.txt
*.sopcinfo *.sopcinfo
**/*.elf
**/*.bin
**/*.dat

132
fw/SummerCart64.qsf
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@ -46,33 +46,14 @@ set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name VERILOG_FILE picorv32/picorv32.v
set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
set_global_assignment -name SDC_FILE SummerCart64.sdc
set_global_assignment -name SIGNALTAP_FILE stp.stp
set_global_assignment -name SYSTEMVERILOG_FILE btldr/btldr.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_gpio.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_wrapper.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp
# Pin & Location Assignments # Pin & Location Assignments
# ========================== # ==========================
set_location_assignment PIN_6 -to o_usb_clk set_location_assignment PIN_6 -to o_usb_clk
set_location_assignment PIN_7 -to io_usb_miosi[3] set_location_assignment PIN_7 -to io_usb_miosi[2]
set_location_assignment PIN_8 -to io_usb_miosi[2] set_location_assignment PIN_8 -to io_usb_miosi[3]
set_location_assignment PIN_10 -to io_usb_miosi[1] set_location_assignment PIN_10 -to io_usb_miosi[0]
set_location_assignment PIN_11 -to io_usb_miosi[0] set_location_assignment PIN_11 -to io_usb_miosi[1]
set_location_assignment PIN_12 -to i_uart_rxd set_location_assignment PIN_12 -to i_uart_rxd
set_location_assignment PIN_13 -to o_uart_txd set_location_assignment PIN_13 -to o_uart_txd
set_location_assignment PIN_14 -to i_uart_cts set_location_assignment PIN_14 -to i_uart_cts
@ -157,9 +138,9 @@ set_location_assignment PIN_132 -to io_flash_dq[3]
set_location_assignment PIN_134 -to o_flash_cs set_location_assignment PIN_134 -to o_flash_cs
set_location_assignment PIN_135 -to io_flash_dq[1] set_location_assignment PIN_135 -to io_flash_dq[1]
set_location_assignment PIN_136 -to io_flash_dq[2] set_location_assignment PIN_136 -to io_flash_dq[2]
set_location_assignment PIN_138 -to i_usb_powered set_location_assignment PIN_138 -to i_usb_pwren
set_location_assignment PIN_140 -to i_usb_miso set_location_assignment PIN_140 -to o_usb_cs
set_location_assignment PIN_141 -to o_usb_cs set_location_assignment PIN_141 -to i_usb_miso
# Classic Timing Assignments # Classic Timing Assignments
# ========================== # ==========================
@ -223,51 +204,82 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# Pin & Location Assignments # Pin & Location Assignments
# ========================== # ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_clk set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_clk
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_cs set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to o_usb_cs
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[0] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[1] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[2] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[3] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_usb_miosi[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[0] set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to io_n64_pi_ad[*]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[1] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[2] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[3] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[0] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_usb_miosi[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[1] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to io_n64_pi_ad[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[2] set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[0]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[3] set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_usb_miso set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_usb_miosi[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_usb_miso
set_instance_assignment -name FAST_INPUT_REGISTER ON -to io_n64_pi_ad[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_aleh
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_alel
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_read
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_pi_write
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_reset
set_instance_assignment -name FAST_INPUT_REGISTER ON -to i_n64_nmi
# Fitter Assignments # Fitter Assignments
# ================== # ==================
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_nmi
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_aleh
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_alel
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_read
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_pi_write
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_reset
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n64_si_clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_n64_si_dq
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_irq set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to o_n64_irq
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[0] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[1] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[2] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[3] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_usb_miosi[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_miso set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_miso
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_usb_pwren
# start DESIGN_PARTITION(Top) # start DESIGN_PARTITION(Top)
# --------------------------- # ---------------------------
# Incremental Compilation Assignments # Incremental Compilation Assignments
# =================================== # ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top) # end DESIGN_PARTITION(Top)
# ------------------------- # -------------------------
# end ENTITY(SummerCart64) # end ENTITY(SummerCart64)
# ------------------------ # ------------------------
set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys
set_global_assignment -name VERILOG_FILE picorv32/picorv32.v
set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
set_global_assignment -name SDC_FILE SummerCart64.sdc
set_global_assignment -name SIGNALTAP_FILE stp.stp
set_global_assignment -name SYSTEMVERILOG_FILE btldr/btldr.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_gpio.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_i2c.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_ram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_soc.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_uart.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_usb.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_wrapper.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

8
fw/btldr/Makefile
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@ -18,19 +18,19 @@ FLAGS=\
all: btldr.bin btldr.sv print_size all: btldr.bin btldr.sv print_size
btldr.elf: btldr.ld btldr.c btldr.elf: btldr.ld btldr.c
$(CROSS)gcc $(FLAGS) btldr.c -o btldr.elf @$(CROSS)gcc $(FLAGS) btldr.c -o btldr.elf
btldr.bin: btldr.elf btldr.bin: btldr.elf
$(CROSS)objcopy -O binary btldr.elf btldr.bin @$(CROSS)objcopy -O binary btldr.elf btldr.bin
btldr.sv: btldr.bin btldr.sv: btldr.bin
python3 bin2sv.py btldr.bin btldr_template.sv btldr.sv @python3 bin2sv.py btldr.bin btldr_template.sv btldr.sv
print_size: print_size:
@echo 'Size of target .elf file:' @echo 'Size of target .elf file:'
$(CROSS)size -B btldr.elf $(CROSS)size -B btldr.elf
clean: clean:
rm -f btldr.sv btldr.bin btldr.elf @rm -f btldr.sv btldr.bin btldr.elf
.PHONY: clean .PHONY: clean

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fw/btldr/btldr.bin
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13
fw/btldr/btldr.c
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@ -2,15 +2,20 @@
int reset_handler (void) { int reset_handler (void) {
io8_t pointer = &RAM; io8_t pointer = &RAM;
uint32_t length = 0;
while (!(USB_SR & USB_SR_TXE)); while (!(USB_SR & USB_SR_TXE));
USB_DR = '>'; USB_DR = '>';
for (int i = 0; i < 4; i++) {
while (!(USB_SR & USB_SR_RXNE));
length |= (USB_DR << (i * 8));
}
while (1) { while (1) {
if (USB_SR & USB_SR_RXNE) { while (!(USB_SR & USB_SR_RXNE));
*pointer++ = USB_DR; *pointer++ = USB_DR;
} if ((uint32_t)pointer == length) {
if ((uint32_t)pointer == (24 * 1024)) {
__asm__("call 0"); __asm__("call 0");
} }
} }

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fw/btldr/btldr.elf
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4
fw/btldr/btldr.h
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@ -9,10 +9,6 @@ typedef volatile uint8_t * io8_t;
typedef volatile uint32_t * io32_t; typedef volatile uint32_t * io32_t;
#define RAM (*((io8_t) 0x00000000)) #define RAM (*((io8_t) 0x00000000))
#define GPIO (*((io32_t) 0x20000000))
#define GPIO_O (*((io8_t) 0x20000000))
#define GPIO_I (*((io8_t) 0x20000001))
#define GPIO_OE (*((io8_t) 0x20000002))
#define USB_SR (*((io8_t) 0x40000000)) #define USB_SR (*((io8_t) 0x40000000))
#define USB_DR (*((io8_t) 0x40000004)) #define USB_DR (*((io8_t) 0x40000004))

30
fw/btldr/btldr.ld
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@ -1,40 +1,16 @@
MEMORY MEMORY
{ {
ram (rwx) : org = 0x00000000, len = 24k rom (rx) : org = 0x10000000, len = 128
rom (rx) : org = 0x10000000, len = 1k
} }
__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16; ENTRY(reset_handler)
ENTRY(reset_handler);
SECTIONS SECTIONS
{ {
.text : .rom :
{ {
. = ALIGN(4); . = ALIGN(4);
*(.text .text* .rodata .rodata* .srodata .srodata*) *(.text .text* .rodata .rodata* .srodata .srodata*)
. = ALIGN(4); . = ALIGN(4);
} > rom AT > rom } > rom AT > rom
.data :
{
. = ALIGN(4);
__data_init_start = LOADADDR(.data);
__data_start = .;
*(.data .data.* .sdata .stada.*);
. = ALIGN(4);
__data_end = .;
} > ram AT > rom
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss .bss.* .sbss .sbss.*)
. = ALIGN(4);
*(COMMON);
. = ALIGN(4);
__bss_end = .;
} > ram AT > ram
} }

39
fw/btldr/btldr.sv
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@ -1,39 +0,0 @@
module cpu_bootloader (if_cpu_bus bus);
always_ff @(posedge bus.clk) begin
bus.ack <= 1'b0;
if (bus.request) begin
bus.ack <= 1'b1;
end
end
always_comb begin
bus.rdata = 32'd0;
if (bus.ack) begin
case (bus.address[6:2])
0: bus.rdata = 32'h40000737;
1: bus.rdata = 32'h00074783;
2: bus.rdata = 32'h0027f793;
3: bus.rdata = 32'hfe078ce3;
4: bus.rdata = 32'h03e00793;
5: bus.rdata = 32'h00f70223;
6: bus.rdata = 32'h400006b7;
7: bus.rdata = 32'h00000793;
8: bus.rdata = 32'h00006637;
9: bus.rdata = 32'h0006c703;
10: bus.rdata = 32'h00177713;
11: bus.rdata = 32'h00070a63;
12: bus.rdata = 32'h0046c703;
13: bus.rdata = 32'h00178793;
14: bus.rdata = 32'h0ff77713;
15: bus.rdata = 32'hfee78fa3;
16: bus.rdata = 32'hfec792e3;
17: bus.rdata = 32'hf0000097;
18: bus.rdata = 32'hfbc080e7;
19: bus.rdata = 32'hfd9ff06f;
default: bus.rdata = 32'd0;
endcase
end
end
endmodule

2
fw/btldr/btldr_template.sv
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@ -3,7 +3,6 @@ module cpu_bootloader (if_cpu_bus bus);
always_ff @(posedge bus.clk) begin always_ff @(posedge bus.clk) begin
bus.ack <= 1'b0; bus.ack <= 1'b0;
if (bus.request) begin if (bus.request) begin
bus.ack <= 1'b1; bus.ack <= 1'b1;
end end
@ -11,7 +10,6 @@ module cpu_bootloader (if_cpu_bus bus);
always_comb begin always_comb begin
bus.rdata = 32'd0; bus.rdata = 32'd0;
if (bus.ack) begin if (bus.ack) begin
case (bus.address[6:2]){rom_formatted} case (bus.address[6:2]){rom_formatted}
default: bus.rdata = 32'd0; default: bus.rdata = 32'd0;

9
fw/cntrllr/Makefile
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@ -17,16 +17,17 @@ FLAGS=\
all: cntrllr.bin print_size all: cntrllr.bin print_size
cntrllr.elf: cntrllr.ld main.c rtc.c startup.S cntrllr.elf: cntrllr.ld main.c rtc.c startup.S
$(CROSS)gcc $(FLAGS) -Tcntrllr.ld main.c rtc.c startup.S -o cntrllr.elf @$(CROSS)gcc $(FLAGS) -Tcntrllr.ld main.c rtc.c startup.S -o cntrllr.elf
cntrllr.bin: cntrllr.elf cntrllr.bin: cntrllr.elf
$(CROSS)objcopy -O binary --gap-fill 0xFF --pad-to 0x6000 cntrllr.elf cntrllr.bin @$(CROSS)objcopy -O binary --gap-fill 0xFF --pad-to 0x4004 cntrllr.elf cntrllr.bin
print_size: print_size:
@echo 'Size of target .elf file:' @echo 'Size of target .elf file:'
$(CROSS)size -B cntrllr.elf @$(CROSS)size -B cntrllr.elf
@echo $(shell $(CROSS)size -B cntrllr.elf | awk 'NR==2 { printf "\nTotal memory used: %.2f%%\n",(100/(16*1024))*($$4-4) }')
clean: clean:
rm -f cntrllr.bin cntrllr.elf @rm -f cntrllr.bin cntrllr.elf
.PHONY: clean .PHONY: clean

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fw/cntrllr/cntrllr.bin
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fw/cntrllr/cntrllr.elf
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14
fw/cntrllr/cntrllr.ld
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@ -1,23 +1,29 @@
MEMORY MEMORY
{ {
ram (rwx) : org = 0x00000000, len = 24k ram (rwx) : org = 0x00000000, len = 16k
} }
__ram_size = LENGTH(ram);
__stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16; __stack_pointer = ORIGIN(ram) + LENGTH(ram) - 16;
ENTRY(reset_handler) ENTRY(reset_handler)
SECTIONS SECTIONS
{ {
.memory : .metadata :
{
KEEP(*(.rodata.metadata));
}
.ram ORIGIN(ram) :
{ {
. = ALIGN(4); . = ALIGN(4);
*(.reset); *(.text.startup);
. = ALIGN(4); . = ALIGN(4);
*(.text .text* .rodata .rodata* .srodata .srodata*); *(.text .text* .rodata .rodata* .srodata .srodata*);
. = ALIGN(4); . = ALIGN(4);
*(.bss .bss.* .sbss .sbss.*); *(.bss .bss.* .sbss .sbss.*);
. = ALIGN(4); . = ALIGN(4);
*(.data .data.* .sdata .stada.*); *(.data .data.* .sdata .stada.*);
} > ram } > ram AT > ram
} }

4
fw/cntrllr/main.c
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@ -76,8 +76,8 @@ __NAKED__ int main (void) {
while (counter++ < 0x0003FFFF); while (counter++ < 0x0003FFFF);
counter = 0; counter = 0;
if (UART_SR & UART_SR_RXNE) { if (USB_SR & USB_SR_RXNE) {
rtc_new_data[index++] = UART_DR; rtc_new_data[index++] = USB_DR;
if (index == 7) { if (index == 7) {
index = 0; index = 0;
rtc_set_time(rtc_new_data); rtc_set_time(rtc_new_data);

6
fw/cntrllr/startup.S
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@ -1,4 +1,8 @@
.section .reset .section .rodata.metadata
metadata:
.word __ram_size
.section .text.startup
.global reset_handler .global reset_handler
reset_handler: reset_handler:
la sp, __stack_pointer la sp, __stack_pointer

9
fw/cntrllr/sys.h
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@ -17,8 +17,10 @@ typedef volatile uint32_t * io32_t;
#define GPIO_OE (*((io8_t) 0x20000002)) #define GPIO_OE (*((io8_t) 0x20000002))
#define I2C_SR (*((io8_t) 0x30000000)) #define I2C_SR (*((io8_t) 0x30000000))
#define I2C_DR (*((io8_t) 0x30000004)) #define I2C_DR (*((io8_t) 0x30000004))
#define UART_SR (*((io8_t) 0x40000000)) #define USB_SR (*((io8_t) 0x40000000))
#define UART_DR (*((io8_t) 0x40000004)) #define USB_DR (*((io8_t) 0x40000004))
#define UART_SR (*((io8_t) 0x50000000))
#define UART_DR (*((io8_t) 0x50000004))
#define I2C_SR_START (1 << 0) #define I2C_SR_START (1 << 0)
#define I2C_SR_STOP (1 << 1) #define I2C_SR_STOP (1 << 1)
@ -27,6 +29,9 @@ typedef volatile uint32_t * io32_t;
#define I2C_SR_BUSY (1 << 4) #define I2C_SR_BUSY (1 << 4)
#define I2C_ADDR_READ (1 << 0) #define I2C_ADDR_READ (1 << 0)
#define USB_SR_RXNE (1 << 0)
#define USB_SR_TXE (1 << 1)
#define UART_SR_RXNE (1 << 0) #define UART_SR_RXNE (1 << 0)
#define UART_SR_TXE (1 << 1) #define UART_SR_TXE (1 << 1)

1
fw/cntrllr/time.dat
View File

@ -1 +0,0 @@
0"!

118
fw/rtl/SummerCart64.sv
View File

@ -5,7 +5,7 @@ module SummerCart64 (
output o_usb_cs, output o_usb_cs,
input i_usb_miso, input i_usb_miso,
inout [3:0] io_usb_miosi, inout [3:0] io_usb_miosi,
input i_usb_powered, input i_usb_pwren,
input i_uart_rxd, input i_uart_rxd,
output o_uart_txd, output o_uart_txd,
@ -44,29 +44,121 @@ module SummerCart64 (
output o_led output o_led
); );
if_system system_if (.in_clk(i_clk)); logic [7:0] gpio_o;
system system_inst (.system_if(system_if)); logic [7:0] gpio_i;
logic [7:0] gpio_oe;
wire [7:0] gpio_o; always_comb begin
wire [7:0] gpio_i; o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ;
wire [7:0] gpio_oe; o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ;
gpio_i = {4'b0000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led};
end
assign o_led = gpio_oe[0] ? gpio_o[0] : 1'bZ; if_system sys (
assign o_n64_irq = gpio_oe[1] ? gpio_o[1] : 1'bZ; .in_clk(i_clk),
assign gpio_i = {4'b0000, i_n64_nmi, i_n64_reset, o_n64_irq, o_led}; .n64_reset(i_n64_reset),
.n64_nmi(i_n64_nmi)
);
system system_inst (
.sys(sys)
);
cpu_soc cpu_soc_inst ( cpu_soc cpu_soc_inst (
.system_if(system_if), .sys(sys),
.gpio_o(gpio_o), .gpio_o(gpio_o),
.gpio_i(gpio_i), .gpio_i(gpio_i),
.gpio_oe(gpio_oe), .gpio_oe(gpio_oe),
.i2c_scl(io_rtc_scl),
.i2c_sda(io_rtc_sda),
.usb_clk(o_usb_clk), .usb_clk(o_usb_clk),
.usb_cs(o_usb_cs), .usb_cs(o_usb_cs),
.usb_miso(i_usb_miso), .usb_miso(i_usb_miso),
.usb_miosi(io_usb_miosi), .usb_miosi(io_usb_miosi),
.usb_powered(i_usb_powered), .usb_pwren(i_usb_pwren),
.i2c_scl(io_rtc_scl),
.i2c_sda(io_rtc_sda) .uart_rxd(i_uart_rxd),
.uart_txd(o_uart_txd),
.uart_cts(i_uart_cts),
.uart_rts(o_uart_rts)
); );
logic n64_request;
logic n64_ack;
logic n64_write;
logic [31:0] n64_address;
logic [15:0] n64_wdata;
logic [15:0] n64_rdata;
n64_pi n64_pi_inst (
.sys(sys),
.n64_pi_alel(i_n64_pi_alel),
.n64_pi_aleh(i_n64_pi_aleh),
.n64_pi_read(i_n64_pi_read),
.n64_pi_write(i_n64_pi_write),
.n64_pi_ad(io_n64_pi_ad),
.request(n64_request),
.ack(n64_ack),
.write(n64_write),
.address(n64_address),
.wdata(n64_wdata),
.rdata(n64_rdata)
);
logic flash_request;
logic [31:0] flash_rdata;
logic flash_busy;
logic flash_ack;
logic in_address;
logic dummy_ack;
intel_flash intel_flash_inst (
.clock(sys.clk),
.reset_n(~sys.reset),
.avmm_data_addr(n64_address[31:2]),
.avmm_data_read((n64_ack && in_address) || flash_request),
.avmm_data_readdata(flash_rdata),
.avmm_data_waitrequest(flash_busy),
.avmm_data_readdatavalid(flash_ack),
.avmm_data_burstcount(2'd1)
);
always_ff @(posedge sys.clk) begin
dummy_ack <= 1'b0;
if (sys.reset) begin
flash_request <= 1'b0;
end else begin
if (!flash_busy) begin
flash_request <= 1'b0;
end
if (n64_request && in_address) begin
flash_request <= 1'b1;
end
if (!in_address && n64_request) begin
dummy_ack <= 1'b1;
end
end
end
always_comb begin
in_address = n64_address < 32'h10008000;
n64_rdata = n64_address[1] ? {flash_rdata[23:16], flash_rdata[31:24]} : {flash_rdata[7:0], flash_rdata[15:8]};
if (!in_address) n64_rdata = 32'd0;
n64_ack = 1'b0;
if (in_address) begin
n64_ack = flash_ack;
end else begin
n64_ack = dummy_ack;
end
end
endmodule endmodule

26
fw/rtl/cpu/cpu_ram.sv
View File

@ -1,10 +1,10 @@
module cpu_ram(if_cpu_bus bus); module cpu_ram(if_cpu_bus bus);
wire bank; logic bank;
reg [3:0][7:0] ram_1 [0:4095]; logic [3:0][7:0] ram_1 [0:4095];
reg [3:0][7:0] ram_2 [0:2047]; // logic [3:0][7:0] ram_2 [0:2047];
reg [31:0] q_1, q_2; logic [31:0] q_1;//, q_2;
wire [31:0] q; // logic [31:0] q;
assign bank = bus.address[14]; assign bank = bus.address[14];
@ -12,7 +12,7 @@ module cpu_ram(if_cpu_bus bus);
bus.rdata = 32'd0; bus.rdata = 32'd0;
if (bus.ack) begin if (bus.ack) begin
bus.rdata = q_1; bus.rdata = q_1;
if (bank) bus.rdata = q_2; // if (bank) bus.rdata = q_2;
end end
end end
@ -32,13 +32,13 @@ module cpu_ram(if_cpu_bus bus);
if (bus.wmask[3]) ram_1[bus.address[13:2]][3] <= bus.wdata[31:24]; if (bus.wmask[3]) ram_1[bus.address[13:2]][3] <= bus.wdata[31:24];
end end
q_2 <= ram_2[bus.address[12:2]]; // q_2 <= ram_2[bus.address[12:2]];
if (bus.request & bank) begin // if (bus.request & bank) begin
if (bus.wmask[0]) ram_2[bus.address[12:2]][0] <= bus.wdata[7:0]; // if (bus.wmask[0]) ram_2[bus.address[12:2]][0] <= bus.wdata[7:0];
if (bus.wmask[1]) ram_2[bus.address[12:2]][1] <= bus.wdata[15:8]; // if (bus.wmask[1]) ram_2[bus.address[12:2]][1] <= bus.wdata[15:8];
if (bus.wmask[2]) ram_2[bus.address[12:2]][2] <= bus.wdata[23:16]; // if (bus.wmask[2]) ram_2[bus.address[12:2]][2] <= bus.wdata[23:16];
if (bus.wmask[3]) ram_2[bus.address[12:2]][3] <= bus.wdata[31:24]; // if (bus.wmask[3]) ram_2[bus.address[12:2]][3] <= bus.wdata[31:24];
end // end
end end
endmodule endmodule

32
fw/rtl/cpu/cpu_soc.sv
View File

@ -1,18 +1,23 @@
module cpu_soc ( module cpu_soc (
if_system.sys system_if, if_system.sys sys,
input [7:0] gpio_i, input [7:0] gpio_i,
output [7:0] gpio_o, output [7:0] gpio_o,
output [7:0] gpio_oe, output [7:0] gpio_oe,
inout i2c_scl,
inout i2c_sda,
output usb_clk, output usb_clk,
output usb_cs, output usb_cs,
input usb_miso, input usb_miso,
inout [3:0] usb_miosi, inout [3:0] usb_miosi,
input usb_powered, input usb_pwren,
inout i2c_scl, input uart_rxd,
inout i2c_sda output uart_txd,
input uart_cts,
output uart_rts
); );
enum bit [3:0] { enum bit [3:0] {
@ -21,14 +26,15 @@ module cpu_soc (
GPIO, GPIO,
I2C, I2C,
USB, USB,
UART,
__NUM_DEVICES __NUM_DEVICES
} e_address_map; } e_address_map;
if_cpu_bus #( if_cpu_bus #(
.NUM_DEVICES(__NUM_DEVICES) .NUM_DEVICES(__NUM_DEVICES)
) bus ( ) bus (
.clk(system_if.clk), .clk(sys.clk),
.reset(system_if.reset) .reset(sys.reset)
); );
cpu_wrapper # ( cpu_wrapper # (
@ -59,13 +65,23 @@ module cpu_soc (
); );
cpu_usb cpu_usb_inst ( cpu_usb cpu_usb_inst (
.system_if(system_if), .sys(sys),
.bus(bus.at[USB].device), .bus(bus.at[USB].device),
.usb_clk(usb_clk), .usb_clk(usb_clk),
.usb_cs(usb_cs), .usb_cs(usb_cs),
.usb_miso(usb_miso), .usb_miso(usb_miso),
.usb_miosi(usb_miosi), .usb_miosi(usb_miosi),
.usb_powered(usb_powered) .usb_pwren(usb_pwren)
);
cpu_uart #(
.BAUD_RATE(1_000_000)
) cpu_uart_inst (
.bus(bus.at[UART].device),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.uart_cts(uart_cts),
.uart_rts(uart_rts)
); );
endmodule endmodule

142
fw/rtl/cpu/cpu_uart.sv
View File

@ -1,81 +1,89 @@
// module cpu_uart ( module cpu_uart # (
// if_system.sys system_if, parameter BAUD_RATE = 1_000_000
// if_cpu_bus_out cpu_bus_if, ) (
// if_cpu_bus_in cpu_uart_if, if_cpu_bus bus,
// output ftdi_clk, input uart_rxd,
// output ftdi_si, output uart_txd,
// input ftdi_so, input uart_cts,
// input ftdi_cts output uart_rts
// ); );
// wire request; localparam BAUD_GEN_VALUE = int'(100_000_000 / BAUD_RATE) - 1'd1;
// wire [31:0] rdata;
// cpu_bus_glue #(.ADDRESS(4'hD)) cpu_bus_glue_uart_inst ( typedef enum bit [1:0] {
// .*, S_TX_IDLE,
// .cpu_peripheral_if(cpu_uart_if), S_TX_DATA
// .request(request), } e_tx_state;
// .rdata(rdata)
// );
// reg rx_ready; e_tx_state tx_state;
// wire tx_busy; logic [7:0] tx_data;
// reg [7:0] rx_data; logic tx_start;
// reg [7:0] tx_data;
// always_comb begin always_comb begin
// case (cpu_bus_if.address[3:2]) bus.rdata = 32'd0;
// 0: rdata = {30'd0, ~tx_busy, ~rx_ready}; if (bus.ack) begin
// 1: rdata = {24'd0, rx_data}; case (bus.address[2:2])
// 2: rdata = {24'd0, tx_data}; 0: bus.rdata = {30'd0, tx_state == S_TX_IDLE, 1'b0};
// default: rdata = 32'd0; default: bus.rdata = 32'd0;
// endcase endcase
// end end
end
// wire rx_valid; always_ff @(posedge bus.clk) begin
// reg tx_valid; bus.ack <= 1'b0;
// wire [7:0] f_rx_data; tx_start <= 1'b0;
// always_ff @(posedge system_if.clk) begin if (bus.request) begin
// tx_valid <= 1'b0; bus.ack <= 1'b1;
// if (rx_valid) begin case (bus.address[2:2])
// rx_ready <= 1'b0; 2'd1: if (bus.wmask[0]) begin
// rx_data <= f_rx_data; tx_data <= bus.wdata[7:0];
// end tx_start <= 1'b1;
end
endcase
end
end
// if (system_if.reset) begin logic [6:0] tx_baud_counter;
// rx_ready <= 1'b1; logic [3:0] tx_bit_counter;
// end else if (request) begin logic [9:0] tx_shifter;
// if (cpu_bus_if.wstrb[0] && cpu_bus_if.address[3:2] == 2'd2 && !tx_busy) begin
// tx_valid <= 1'b1;
// tx_data <= cpu_bus_if.wdata[7:0];
// end
// if (cpu_bus_if.address[3:2] == 2'd1) begin
// rx_ready <= 1'b1;
// end
// end
// end
// usb_ftdi_fsi usb_ftdi_fsi_inst ( always_ff @(posedge bus.clk) begin
// .i_clk(system_if.clk), tx_baud_counter <= tx_baud_counter + 1'd1;
// .i_reset(system_if.reset), uart_txd <= tx_shifter[0];
// .o_ftdi_clk(ftdi_clk), if (bus.reset) begin
// .o_ftdi_si(ftdi_si), tx_state <= S_TX_IDLE;
// .i_ftdi_so(ftdi_so), tx_shifter <= 10'h3FF;
// .i_ftdi_cts(ftdi_cts), end else begin
case (tx_state)
S_TX_IDLE: begin
if (tx_start) begin
tx_state <= S_TX_DATA;
tx_baud_counter <= 7'd0;
tx_bit_counter <= 4'd0;
tx_shifter <= {1'b1, tx_data, 1'b0};
end
end
// .i_rx_ready(rx_ready), S_TX_DATA: begin
// .o_rx_valid(rx_valid), if (tx_baud_counter == BAUD_GEN_VALUE) begin
// // .o_rx_channel(1'bX), tx_baud_counter <= 7'd0;
// .o_rx_data(f_rx_data), tx_bit_counter <= tx_bit_counter + 1'd1;
tx_shifter <= {1'b1, tx_shifter[9:1]};
if (tx_bit_counter == 4'd9) begin
tx_state <= S_TX_IDLE;
end
end
end
// .o_tx_busy(tx_busy), default: begin
// .i_tx_valid(tx_valid), tx_state <= S_TX_IDLE;
// .i_tx_channel(1'b1), end
// .i_tx_data(tx_data) endcase
// ); end
end
// endmodule endmodule

24
fw/rtl/cpu/cpu_usb.sv
View File

@ -1,23 +1,23 @@
module cpu_usb ( module cpu_usb (
if_system system_if, if_system sys,
if_cpu_bus bus, if_cpu_bus bus,
output usb_clk, output usb_clk,
output usb_cs, output usb_cs,
input usb_miso, input usb_miso,
inout [3:0] usb_miosi, inout [3:0] usb_miosi,
input usb_powered input usb_pwren
); );
reg rx_flush; logic rx_flush;
wire rx_empty; logic rx_empty;
reg rx_read; logic rx_read;
wire [7:0] rx_rdata; logic [7:0] rx_rdata;
reg tx_flush; logic tx_flush;
wire tx_full; logic tx_full;
reg tx_write; logic tx_write;
reg [7:0] tx_wdata; logic [7:0] tx_wdata;
always_comb begin always_comb begin
bus.rdata = 32'd0; bus.rdata = 32'd0;
@ -61,13 +61,13 @@ module cpu_usb (
end end
usb_ft1248 usb_ft1248_inst ( usb_ft1248 usb_ft1248_inst (
.system_if(system_if), .sys(sys),
.usb_clk(usb_clk), .usb_clk(usb_clk),
.usb_cs(usb_cs), .usb_cs(usb_cs),
.usb_miso(usb_miso), .usb_miso(usb_miso),
.usb_miosi(usb_miosi), .usb_miosi(usb_miosi),
.usb_powered(usb_powered), .usb_pwren(usb_pwren),
.rx_flush(rx_flush), .rx_flush(rx_flush),
.rx_empty(rx_empty), .rx_empty(rx_empty),

26
fw/rtl/intel/flash/intel_flash.qsys
View File

@ -7,17 +7,17 @@
description="" description=""
tags="INTERNAL_COMPONENT=true" tags="INTERNAL_COMPONENT=true"
categories="System" /> categories="System" />
<parameter name="bonusData"><![CDATA[bonusData <parameter name="bonusData"><![CDATA[bonusData
{ {
element onchip_flash_0 element onchip_flash_0
{ {
datum _sortIndex datum _sortIndex
{ {
value = "0"; value = "0";
type = "int"; type = "int";
} }
} }
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M08SCE144C8G" /> <parameter name="device" value="10M08SCE144C8G" />
@ -71,8 +71,8 @@
<parameter name="SECTOR_ACCESS_MODE">Read only,Read only,Hidden,Read only,Read only</parameter> <parameter name="SECTOR_ACCESS_MODE">Read only,Read only,Hidden,Read only,Read only</parameter>
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter> <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter>
<parameter name="initFlashContent" value="true" /> <parameter name="initFlashContent" value="true" />
<parameter name="initializationFileName">btldr/btldr.hex</parameter> <parameter name="initializationFileName">C:/Dev/SummerCollection/sw/bootloader/what/build/SummerLoader64.hex</parameter>
<parameter name="initializationFileNameForSim">btldr/btldr.hex</parameter> <parameter name="initializationFileNameForSim">C:/Dev/SummerCollection/sw/bootloader/what/build/SummerLoader64.hex</parameter>
<parameter name="useNonDefaultInitFile" value="true" /> <parameter name="useNonDefaultInitFile" value="true" />
</module> </module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />

0
fw/rtl/memory/memory_sdram.sv Normal file
View File

165
fw/rtl/n64/n64_pi.sv Normal file
View File

@ -0,0 +1,165 @@
module n64_pi (
if_system.sys sys,
input n64_pi_alel,
input n64_pi_aleh,
input n64_pi_read,
input n64_pi_write,
inout [15:0] n64_pi_ad,
output request,
input ack,
output write,
output [31:0] address,
output [15:0] wdata,
input [15:0] rdata
);
// Control signals input synchronization
logic [2:0] n64_pi_alel_ff;
logic [2:0] n64_pi_aleh_ff;
logic [2:0] n64_pi_read_ff;
logic [2:0] n64_pi_write_ff;
always_ff @(posedge sys.clk) begin
n64_pi_aleh_ff <= {n64_pi_aleh_ff[1:0], n64_pi_aleh};
n64_pi_alel_ff <= {n64_pi_alel_ff[1:0], n64_pi_alel};
n64_pi_read_ff <= {n64_pi_read_ff[1:0], n64_pi_read};
n64_pi_write_ff <= {n64_pi_write_ff[1:0], n64_pi_write};
end
logic pi_reset;
logic pi_aleh;
logic pi_alel;
logic pi_read;
logic pi_read_delayed;
logic pi_write;
logic pi_write_delayed;
always_comb begin
pi_reset = sys.n64_hard_reset;
pi_aleh = n64_pi_aleh_ff[2];
pi_alel = n64_pi_alel_ff[2];
pi_read = n64_pi_read_ff[1];
pi_read_delayed = n64_pi_read_ff[2];
pi_write = n64_pi_write_ff[1];
pi_write_delayed = n64_pi_write_ff[2];
end
// PI bus state and event generator
typedef enum bit [1:0] {
PI_MODE_IDLE = 2'b10,
PI_MODE_HIGH = 2'b11,
PI_MODE_LOW = 2'b01,
PI_MODE_VALID = 2'b00
} e_pi_mode;
e_pi_mode pi_mode;
e_pi_mode last_pi_mode;
logic last_read;
logic last_write;
always_comb begin
pi_mode = e_pi_mode'({pi_aleh, pi_alel});
end
always_ff @(posedge sys.clk) begin
last_pi_mode <= pi_mode;
last_read <= pi_read;
last_write <= pi_write;
end
logic aleh_op;
logic alel_op;
logic read_op;
logic write_op;
always_comb begin
aleh_op = !pi_reset && last_pi_mode != PI_MODE_HIGH && pi_mode == PI_MODE_HIGH;
alel_op = !pi_reset && last_pi_mode == PI_MODE_HIGH && pi_mode == PI_MODE_LOW;
read_op = !pi_reset && pi_mode == PI_MODE_VALID && last_read && !pi_read;
write_op = !pi_reset && pi_mode == PI_MODE_VALID && last_write && !pi_write;
end
// Input and output data sampling
logic [15:0] n64_pi_ad_input;
logic [15:0] n64_pi_ad_output;
logic [15:0] n64_pi_ad_output_data;
logic [15:0] n64_pi_ad_output_data_buffer;
logic n64_pi_ad_output_enable;
logic n64_pi_ad_output_enable_data;
always_comb begin
n64_pi_ad = n64_pi_ad_output_enable ? n64_pi_ad_output : 16'hZZZZ;
n64_pi_ad_output_enable_data = !pi_reset && pi_mode == PI_MODE_VALID && !pi_read_delayed;
end
always_ff @(posedge sys.clk) begin
n64_pi_ad_input <= n64_pi_ad;
n64_pi_ad_output <= n64_pi_ad_output_data;
n64_pi_ad_output_enable <= n64_pi_ad_output_enable_data;
if (read_op) begin
n64_pi_ad_output_data <= n64_pi_ad_output_data_buffer;
end
end
// Internal bus controller
typedef enum bit [0:0] {
S_IDLE,
S_WAIT
} e_state;
e_state state;
logic first_operation;
logic pending_operation;
logic pending_write;
always_ff @(posedge sys.clk) begin
request <= 1'b0;
if (sys.reset || sys.n64_hard_reset || sys.n64_soft_reset) begin
state <= S_IDLE;
first_operation <= 1'b0;
pending_operation <= 1'b0;
end else begin
case (state)
S_IDLE: begin
if (aleh_op) address[31:16] <= n64_pi_ad_input;
if (alel_op) address[15:0] <= {n64_pi_ad_input[15:1], 1'b0};
if (alel_op || read_op || write_op || pending_operation) begin
state <= S_WAIT;
request <= 1'b1;
write <= write_op || (pending_operation && pending_write);
if (!alel_op && !(first_operation && write_op)) begin
address[31:1] <= address[31:1] + 1'd1;
end
wdata <= n64_pi_ad_input;
first_operation <= alel_op;
end
end
S_WAIT: begin
if (ack) begin
state <= S_IDLE;
n64_pi_ad_output_data_buffer <= rdata;
end
if (read_op || write_op) begin
pending_operation <= 1'b1;
pending_write <= write_op;
end
end
default: begin
state <= S_IDLE;
first_operation <= 1'b0;
pending_operation <= 1'b0;
end
endcase
end
end
endmodule

55
fw/rtl/system/system.sv
View File

@ -1,19 +1,31 @@
interface if_system (input in_clk); interface if_system (
input in_clk,
input n64_reset,
input n64_nmi
);
logic clk; logic clk;
logic sdram_clk; logic sdram_clk;
logic reset; logic reset;
logic n64_soft_reset;
logic n64_hard_reset;
modport pll ( modport internal (
input in_clk, input in_clk,
input n64_reset,
input n64_nmi,
output clk, output clk,
output sdram_clk, output sdram_clk,
output reset output reset,
output n64_soft_reset,
output n64_hard_reset
); );
modport sys ( modport sys (
input clk, input clk,
input reset input reset,
input n64_soft_reset,
input n64_hard_reset
); );
modport sdram ( modport sdram (
@ -23,23 +35,34 @@ interface if_system (input in_clk);
endinterface endinterface
module system (if_system.pll system_if); module system (if_system.internal sys);
wire locked; logic locked;
wire external_reset; logic external_reset;
logic [1:0] n64_reset_ff;
assign system_if.reset = ~locked | external_reset; logic [1:0] n64_nmi_ff;
intel_pll intel_pll_inst ( intel_pll intel_pll_inst (
.inclk0(system_if.in_clk), .inclk0(sys.in_clk),
.c0(system_if.clk), .c0(sys.clk),
.c1(system_if.sdram_clk), .c1(sys.sdram_clk),
.locked(locked) .locked(locked)
); );
// intel_snp intel_snp_inst ( intel_snp intel_snp_inst (
// .source(external_reset), .source(external_reset),
// .source_clk(system_if.clk) .source_clk(sys.clk)
// ); );
always_ff @(posedge sys.clk) begin
n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset};
n64_nmi_ff <= {n64_nmi_ff[0], sys.n64_nmi};
end
always_comb begin
sys.reset = ~locked | external_reset;
sys.n64_hard_reset <= ~n64_reset_ff[1];
sys.n64_soft_reset <= ~n64_nmi_ff[1];
end
endmodule endmodule

18
fw/rtl/usb/usb_ft1248.sv
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@ -1,11 +1,11 @@
module usb_ft1248 ( module usb_ft1248 (
if_system.sys system_if, if_system.sys sys,
output usb_clk, output usb_clk,
output usb_cs, output usb_cs,
input usb_miso, input usb_miso,
inout [3:0] usb_miosi, inout [3:0] usb_miosi,
input usb_powered, input usb_pwren,
input rx_flush, input rx_flush,
output rx_empty, output rx_empty,
@ -32,7 +32,7 @@ module usb_ft1248 (
wire [7:0] tx_rdata; wire [7:0] tx_rdata;
fifo8 fifo_8_rx_inst ( fifo8 fifo_8_rx_inst (
.clock(system_if.clk), .clock(sys.clk),
.sclr(rx_flush), .sclr(rx_flush),
.empty(rx_empty), .empty(rx_empty),
@ -47,7 +47,7 @@ module usb_ft1248 (
); );
fifo8 fifo_8_tx_inst ( fifo8 fifo_8_tx_inst (
.clock(system_if.clk), .clock(sys.clk),
.sclr(tx_flush), .sclr(tx_flush),
.empty(tx_empty), .empty(tx_empty),
@ -86,8 +86,8 @@ module usb_ft1248 (
reg [3:0] clock_divider; reg [3:0] clock_divider;
wire rising_edge = clock_divider[1]; wire rising_edge = clock_divider[1];
always_ff @(posedge system_if.clk) begin always_ff @(posedge sys.clk) begin
if (system_if.reset || state == S_TRY_RX || state == S_TRY_TX) begin if (sys.reset || state == S_TRY_RX || state == S_TRY_TX) begin
clock_divider <= 4'b0001; clock_divider <= 4'b0001;
end else begin end else begin
clock_divider <= {clock_divider[2:0], clock_divider[3]}; clock_divider <= {clock_divider[2:0], clock_divider[3]};
@ -120,7 +120,7 @@ module usb_ft1248 (
usb_miosi = miosi_output_enable ? miosi_output : 4'bZZZZ; usb_miosi = miosi_output_enable ? miosi_output : 4'bZZZZ;
end end
always_ff @(posedge system_if.clk) begin always_ff @(posedge sys.clk) begin
clk_output <= clk_data; clk_output <= clk_data;
cs_output <= cs_data; cs_output <= cs_data;
miosi_input <= usb_miosi; miosi_input <= usb_miosi;
@ -133,11 +133,11 @@ module usb_ft1248 (
reg is_write; reg is_write;
always_ff @(posedge system_if.clk) begin always_ff @(posedge sys.clk) begin
rx_write <= 1'b0; rx_write <= 1'b0;
tx_read <= 1'b0; tx_read <= 1'b0;
if (system_if.reset) begin if (sys.reset) begin
state <= S_TRY_RX; state <= S_TRY_RX;
cs_data <= 1'b1; cs_data <= 1'b1;
miosi_output_enable_data <= 1'b0; miosi_output_enable_data <= 1'b0;

673
fw/stp.stp
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File diff suppressed because one or more lines are too long

1
sw/bootloader/.gitignore vendored
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@ -1 +1,2 @@
/build /build
/what

4
sw/bootloader/Makefile
View File

@ -16,7 +16,7 @@ HEADER_NAME = header
PROG_NAME = SummerLoader64 PROG_NAME = SummerLoader64
ROM_SIZE = 1k ROM_SIZE = 32k
SOURCE_DIR = src SOURCE_DIR = src
BUILD_DIR = build BUILD_DIR = build
@ -31,7 +31,7 @@ VPATH = $(SRC_DIRS)
COMMONFLAGS = -march=vr4300 -mtune=vr4300 COMMONFLAGS = -march=vr4300 -mtune=vr4300
ASFLAGS = $(COMMONFLAGS) ASFLAGS = $(COMMONFLAGS)
CFLAGS = $(COMMONFLAGS) -std=gnu11 -Os -Wall -I$(ROOTDIR)/mips64-elf/include $(INC_DIRS) CFLAGS = $(COMMONFLAGS) -std=gnu11 -Os -Wall -I$(ROOTDIR)/mips64-elf/include $(INC_DIRS) -ffunction-sections -fdata-sections -Wl,--gc-sections
LINK_FLAGS = -L$(ROOTDIR)/mips64-elf/lib -ldragon -lc -lm -ldragonsys -Tn64.ld -L./libsc64/lib -lsc64_libdragon LINK_FLAGS = -L$(ROOTDIR)/mips64-elf/lib -ldragon -lc -lm -ldragonsys -Tn64.ld -L./libsc64/lib -lsc64_libdragon
N64_FLAGS = -l $(ROM_SIZE) -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME).z64 N64_FLAGS = -l $(ROM_SIZE) -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME).z64
N64_FLAGS_PADDED = -l 1028k -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME)_padded.z64 N64_FLAGS_PADDED = -l 1028k -h $(HEADER_PATH)/$(HEADER_NAME) -o $(BUILD_DIR)/$(PROG_NAME)_padded.z64

2
sw/bootloader/build.sh
View File

@ -7,4 +7,4 @@ build_in_docker() {
$1 /bin/bash -c "cd /src && make clean && make -f $2 all" $1 /bin/bash -c "cd /src && make clean && make -f $2 all"
} }
build_in_docker "anacierdem/libdragon:latest" "Makefile" build_in_docker "anacierdem/libdragon:6.0.2" "Makefile"

201
sw/bootloader/src/main.c
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@ -29,128 +29,129 @@ static menu_load_error_t convert_error(sc64_sd_fs_error_t sd_fs_error) {
int main(void) { int main(void) {
OS_BOOT_CONFIG->tv_type = TV_NTSC; while (1);
// OS_BOOT_CONFIG->tv_type = TV_NTSC;
if (sc64_get_version() != SC64_CART_VERSION_A) { // if (sc64_get_version() != SC64_CART_VERSION_A) {
loader_display_error_and_halt(E_MENU_ERROR_NOT_SC64, ""); // loader_display_error_and_halt(E_MENU_ERROR_NOT_SC64, "");
} // }
sc64_enable_rom_switch(); // sc64_enable_rom_switch();
uint32_t boot_mode = sc64_get_boot_mode(); // uint32_t boot_mode = sc64_get_boot_mode();
bool skip_menu = (boot_mode & SC64_CART_BOOT_SKIP_MENU); // bool skip_menu = (boot_mode & SC64_CART_BOOT_SKIP_MENU);
bool cic_seed_override = (boot_mode & SC64_CART_BOOT_CIC_SEED_OVERRIDE); // bool cic_seed_override = (boot_mode & SC64_CART_BOOT_CIC_SEED_OVERRIDE);
bool tv_type_override = (boot_mode & SC64_CART_BOOT_TV_TYPE_OVERRIDE); // bool tv_type_override = (boot_mode & SC64_CART_BOOT_TV_TYPE_OVERRIDE);
bool ddipl_override = (boot_mode & SC64_CART_BOOT_DDIPL_OVERRIDE); // bool ddipl_override = (boot_mode & SC64_CART_BOOT_DDIPL_OVERRIDE);
bool rom_loaded = (boot_mode & SC64_CART_BOOT_ROM_LOADED); // bool rom_loaded = (boot_mode & SC64_CART_BOOT_ROM_LOADED);
tv_type_t tv_type = ((boot_mode & SC64_CART_BOOT_TV_TYPE_MASK) >> SC64_CART_BOOT_TV_TYPE_BIT); // tv_type_t tv_type = ((boot_mode & SC64_CART_BOOT_TV_TYPE_MASK) >> SC64_CART_BOOT_TV_TYPE_BIT);
uint16_t cic_seed = ((boot_mode & SC64_CART_BOOT_CIC_SEED_MASK) >> SC64_CART_BOOT_CIC_SEED_BIT); // uint16_t cic_seed = ((boot_mode & SC64_CART_BOOT_CIC_SEED_MASK) >> SC64_CART_BOOT_CIC_SEED_BIT);
if (!skip_menu) { // if (!skip_menu) {
char rom_path[256] = DEFAULT_MENU_FILE_PATH; // char rom_path[256] = DEFAULT_MENU_FILE_PATH;
char save_path[256] = "\0"; // char save_path[256] = "\0";
sc64_sd_fs_error_t sd_fs_error; // sc64_sd_fs_error_t sd_fs_error;
sc64_sd_fs_config_t config = { // sc64_sd_fs_config_t config = {
.rom = rom_path, // .rom = rom_path,
.rom_reload = false, // .rom_reload = false,
.save = save_path, // .save = save_path,
.save_type = 0, // .save_type = 0,
.save_writeback = false, // .save_writeback = false,
.cic_seed = 0xFFFF, // .cic_seed = 0xFFFF,
.tv_type = -1, // .tv_type = -1,
}; // };
sd_fs_error = sc64_sd_fs_init(); // sd_fs_error = sc64_sd_fs_init();
if (sd_fs_error != SC64_SD_FS_OK) { // if (sd_fs_error != SC64_SD_FS_OK) {
loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_init"); // loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_init");
} // }
sd_fs_error = sc64_sd_fs_load_config(CONFIG_FILE_PATH, &config); // sd_fs_error = sc64_sd_fs_load_config(CONFIG_FILE_PATH, &config);
if ((sd_fs_error != SC64_SD_FS_OK) && (sd_fs_error != SC64_SD_FS_NO_FILE)) { // if ((sd_fs_error != SC64_SD_FS_OK) && (sd_fs_error != SC64_SD_FS_NO_FILE)) {
loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_config"); // loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_config");
} // }
if (config.cic_seed != 0xFFFF) { // if (config.cic_seed != 0xFFFF) {
cic_seed_override = true; // cic_seed_override = true;
cic_seed = config.cic_seed; // cic_seed = config.cic_seed;
} // }
if (config.tv_type != -1) { // if (config.tv_type != -1) {
tv_type_override = true; // tv_type_override = true;
tv_type = config.tv_type; // tv_type = config.tv_type;
} // }
if (!rom_loaded || config.rom_reload) { // if (!rom_loaded || config.rom_reload) {
loader_display_logo(); // loader_display_logo();
} // }
if (config.save_type > 0) { // if (config.save_type > 0) {
sc64_disable_eeprom(); // sc64_disable_eeprom();
sc64_disable_sram(); // sc64_disable_sram();
sc64_disable_flashram(); // sc64_disable_flashram();
switch (config.save_type) { // switch (config.save_type) {
case 1: sc64_enable_eeprom(false); break; // case 1: sc64_enable_eeprom(false); break;
case 2: sc64_enable_eeprom(true); break; // case 2: sc64_enable_eeprom(true); break;
case 3: // case 3:
case 4: sc64_enable_sram(); break; // case 4: sc64_enable_sram(); break;
case 5: // case 5:
case 6: sc64_enable_flashram(); break; // case 6: sc64_enable_flashram(); break;
} // }
if (config.save_type >= 3 || config.save_type <= 5) { // if (config.save_type >= 3 || config.save_type <= 5) {
sc64_set_save_address(SC64_SDRAM_SIZE - (128 * 1024)); // sc64_set_save_address(SC64_SDRAM_SIZE - (128 * 1024));
} else if (config.save_type == 6) { // } else if (config.save_type == 6) {
sc64_set_save_address(0x01618000); // sc64_set_save_address(0x01618000);
} // }
if (rom_loaded && (config.save[0] != '\0') && config.save_writeback) { // if (rom_loaded && (config.save[0] != '\0') && config.save_writeback) {
sd_fs_error = sc64_sd_fs_store_save(config.save); // sd_fs_error = sc64_sd_fs_store_save(config.save);
if (sd_fs_error != SC64_SD_FS_OK) { // if (sd_fs_error != SC64_SD_FS_OK) {
loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_store_save"); // loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_store_save");
} // }
} // }
} // }
if (!rom_loaded || config.rom_reload) { // if (!rom_loaded || config.rom_reload) {
sd_fs_error = sc64_sd_fs_load_rom(config.rom); // sd_fs_error = sc64_sd_fs_load_rom(config.rom);
if (sd_fs_error != SC64_SD_FS_OK) { // if (sd_fs_error != SC64_SD_FS_OK) {
loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_rom"); // loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_rom");
} // }
sc64_set_boot_mode(boot_mode | SC64_CART_BOOT_ROM_LOADED); // sc64_set_boot_mode(boot_mode | SC64_CART_BOOT_ROM_LOADED);
} // }
if ((config.save_type > 0) && (config.save[0] != '\0') && !rom_loaded) { // if ((config.save_type > 0) && (config.save[0] != '\0') && !rom_loaded) {
sd_fs_error = sc64_sd_fs_load_save(config.save); // sd_fs_error = sc64_sd_fs_load_save(config.save);
if (sd_fs_error != SC64_SD_FS_OK) { // if (sd_fs_error != SC64_SD_FS_OK) {
loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_save"); // loader_display_error_and_halt(convert_error(sd_fs_error), "sc64_sd_fs_load_save");
} // }
} // }
sc64_sd_fs_deinit(); // sc64_sd_fs_deinit();
if (!rom_loaded || config.rom_reload) { // if (!rom_loaded || config.rom_reload) {
loader_cleanup(); // loader_cleanup();
} // }
} // }
if (ddipl_override) { // if (ddipl_override) {
sc64_enable_ddipl(); // sc64_enable_ddipl();
} else { // } else {
sc64_disable_ddipl(); // sc64_disable_ddipl();
} // }
cart_header_t *cart_header = boot_load_cart_header(ddipl_override); // cart_header_t *cart_header = boot_load_cart_header(ddipl_override);
if (!cic_seed_override) { // if (!cic_seed_override) {
cic_seed = boot_get_cic_seed(cart_header); // cic_seed = boot_get_cic_seed(cart_header);
} // }
if (!tv_type_override) { // if (!tv_type_override) {
tv_type = boot_get_tv_type(cart_header); // tv_type = boot_get_tv_type(cart_header);
} // }
boot(cart_header, cic_seed, tv_type, ddipl_override); // boot(cart_header, cic_seed, tv_type, ddipl_override);
} }

2
sw/libsc64/build.sh
View File

@ -6,6 +6,6 @@ build_in_docker() {
$1 /bin/bash -c "cd /src && make -f $2 all" $1 /bin/bash -c "cd /src && make -f $2 all"
} }
build_in_docker "anacierdem/libdragon:latest" "Makefile.libdragon" build_in_docker "anacierdem/libdragon:6.0.2" "Makefile.libdragon"
build_in_docker "polprzewodnikowy/n64sdkmod:latest" "Makefile.libultra" build_in_docker "polprzewodnikowy/n64sdkmod:latest" "Makefile.libultra"