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timing test

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Polprzewodnikowy 2022-08-24 20:44:20 +02:00
parent 9373fcfe44
commit 27a5bb94f7
2 changed files with 2 additions and 2 deletions
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2
fw/project/lcmxo2/release.sty
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@ -92,7 +92,7 @@
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/> <Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/> <Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/> <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/> <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/> <Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/> <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/> <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>

2
fw/project/lcmxo2/sc64.ldf
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1"> <BaliProject version="3.2" title="sc64" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
<Options/> <Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="debug"> <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="release">
<Options VerilogStandard="System Verilog" def_top="top" top="top"/> <Options VerilogStandard="System Verilog" def_top="top" top="top"/>
<Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog"> <Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/> <Options VerilogStandard="System Verilog"/>