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SD clock stop when RX FIFO is more than half full

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Polprzewodnikowy 2022-09-29 03:03:51 +02:00
parent c475b62197
commit 2ce73c03bf
3 changed files with 15 additions and 2 deletions
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4
fw/rtl/sd/sd_clk.sv
View File

@ -13,7 +13,9 @@ module sd_clk (
logic [7:0] clock_divider;
always_ff @(posedge clk) begin
clock_divider <= clock_divider + 1'd1;
if (!sd_scb.clock_stop) begin
clock_divider <= clock_divider + 1'd1;
end
end
logic selected_clock;

7
fw/rtl/sd/sd_dat.sv
View File

@ -248,6 +248,7 @@ module sd_dat (
crc_shift <= 1'b0;
if (reset || sd_scb.dat_stop) begin
sd_scb.clock_stop <= 1'b0;
sd_dat_oe_data <= 1'b0;
sd_dat_data <= 4'hF;
end else begin
@ -260,6 +261,9 @@ module sd_dat (
end
STATE_RX_WAIT: begin
if (sd_scb.rx_count <= 11'd512) begin
sd_scb.clock_stop <= 1'b0;
end
if (sd_clk_rising) begin
if (!sd_dat_in[0]) begin
counter <= 11'd1;
@ -288,6 +292,9 @@ module sd_dat (
end
end
if (counter == 11'd1041) begin
if ((blocks_remaining > 8'd0) && (sd_scb.rx_count > 11'd512)) begin
sd_scb.clock_stop <= 1'b1;
end
blocks_remaining <= blocks_remaining - 1'd1;
end
end

6
fw/rtl/sd/sd_scb.sv
View File

@ -1,6 +1,7 @@
interface sd_scb ();
logic [1:0] clock_mode;
logic clock_stop;
logic card_busy;
@ -55,7 +56,8 @@ interface sd_scb ();
);
modport clk (
input clock_mode
input clock_mode,
input clock_stop
);
modport cmd (
@ -72,6 +74,8 @@ interface sd_scb ();
);
modport dat (
output clock_stop,
output card_busy,
output rx_count,