good sdram

fw/SummerCart64.qsf

@@ -66,6 +66,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/memory_flash.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/memory_sdram.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_bus.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_pi.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_sdram.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/n64/n64_soc.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/SummerCart64.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv

fw/rtl/SummerCart64.sv

@@ -62,13 +62,22 @@ module SummerCart64 (
 
     if_config cfg ();
 
+    if_dma dma ();
+
     system system_inst (
         .sys(sys)
     );
 
+    intel_gpio_ddro sdram_clk_ddro (
+        .outclock(sys.sdram.sdram_clk),
+        .din({1'b0, 1'b1}),
+        .pad_out(o_sdram_clk)
+    );
+
     n64_soc n64_soc_inst (
         .sys(sys),
         .cfg(cfg),
+        .dma(dma),
 
         .n64_pi_alel(i_n64_pi_alel),
         .n64_pi_aleh(i_n64_pi_aleh),
@@ -79,7 +88,6 @@ module SummerCart64 (
         .n64_si_clk(i_n64_si_clk),
         .n64_si_dq(io_n64_si_dq),
 
-        .sdram_clk(o_sdram_clk),
         .sdram_cs(o_sdram_cs),
         .sdram_ras(o_sdram_ras),
         .sdram_cas(o_sdram_cas),
@@ -92,6 +100,7 @@ module SummerCart64 (
     cpu_soc cpu_soc_inst (
         .sys(sys),
         .cfg(cfg),
+        .dma(dma),
 
         .gpio_o(gpio_o),
         .gpio_i(gpio_i),

fw/rtl/cpu/cpu_soc.sv

@@ -1,6 +1,7 @@
 module cpu_soc (
     if_system.sys sys,
     if_config cfg,
+    if_dma.cpu dma,
 
     input [7:0] gpio_i,
     output [7:0] gpio_o,
@@ -60,6 +61,7 @@ module cpu_soc (
     cpu_usb cpu_usb_inst (
         .sys(sys),
         .bus(bus.at[sc64::ID_CPU_USB].device),
+        .dma(dma),
         .usb_clk(usb_clk),
         .usb_cs(usb_cs),
         .usb_miso(usb_miso),

fw/rtl/cpu/cpu_usb.sv

@@ -1,6 +1,36 @@
+interface if_dma ();
+
+    logic request;
+    logic ack;
+    logic write;
+    logic [31:0] address;
+    logic [15:0] rdata;
+    logic [15:0] wdata;
+
+    modport cpu (
+        output request,
+        input ack,
+        output write,
+        output address,
+        input rdata,
+        output wdata
+    );
+
+    modport device (
+        input request,
+        output ack,
+        input write,
+        input address,
+        output rdata,
+        input wdata
+    );
+
+endinterface
+
 module cpu_usb (
     if_system sys,
     if_cpu_bus bus,
+    if_dma.cpu dma,
 
     output usb_clk,
     output usb_cs,
@@ -19,44 +49,87 @@ module cpu_usb (
     logic tx_write;
     logic [7:0] tx_wdata;
 
-    always_ff @(posedge sys.clk) begin
+    // always_ff @(posedge sys.clk) begin
-        bus.ack <= 1'b0;
+    //     bus.ack <= 1'b0;
-        if (bus.request) begin
+    //     if (bus.request) begin
-            bus.ack <= 1'b1;
+    //         bus.ack <= 1'b1;
-        end        
+    //     end        
-    end
+    // end
 
-    always_comb begin
+    // always_comb begin
-        bus.rdata = 32'd0;
+    //     bus.rdata = 32'd0;
-        if (bus.ack) begin
+    //     if (bus.ack) begin
-            case (bus.address[2:2])
+    //         case (bus.address[2:2])
-                0: bus.rdata = {30'd0, ~tx_full, ~rx_empty};
+    //             0: bus.rdata = {30'd0, ~tx_full, ~rx_empty};
-                1: bus.rdata = {24'd0, rx_rdata};
+    //             1: bus.rdata = {24'd0, rx_rdata};
-                default: bus.rdata = 32'd0;
+    //             default: bus.rdata = 32'd0;
-            endcase
+    //         endcase
-        end
+    //     end
-    end
+    // end
+
+    // always_ff @(posedge sys.clk) begin
+    //     rx_flush <= 1'b0;
+    //     rx_read <= 1'b0;
+
+    //     tx_flush <= 1'b0;
+    //     tx_write <= 1'b0;
+
+    //     if (bus.request) begin
+    //         case (bus.address[2:2])
+    //             2'd0: if (bus.wmask[0]) begin
+    //                 {tx_flush, rx_flush} <= bus.wdata[3:2];
+    //             end
+
+    //             2'd1: if (bus.wmask[0]) begin
+    //                 if (!tx_full) begin
+    //                     tx_write <= 1'b1;
+    //                     tx_wdata <= bus.wdata[7:0];
+    //                 end
+    //             end else begin
+    //                 rx_read <= 1'b1;
+    //             end
+    //         endcase
+    //     end
+    // end
+
+    typedef enum bit [0:0] { 
+        S_IDLE,
+        S_WAIT
+    } e_state;
+
+    e_state state;
+
+    logic byte_counter;
 
     always_ff @(posedge sys.clk) begin
-        rx_flush <= 1'b0;
         rx_read <= 1'b0;
 
-        tx_flush <= 1'b0;
+        if (sys.reset) begin
-        tx_write <= 1'b0;
+            dma.request <= 1'b0;
-
+            dma.write <= 1'b1;
-        if (bus.request) begin
+            dma.address <= 32'd0;
-            case (bus.address[2:2])
+            state <= S_IDLE;
-                2'd0: if (bus.wmask[0]) begin
+            byte_counter <= 1'b0;
-                    {tx_flush, rx_flush} <= bus.wdata[3:2];
-                end
-
-                2'd1: if (bus.wmask[0]) begin
-                    if (!tx_full) begin
-                        tx_write <= 1'b1;
-                        tx_wdata <= bus.wdata[7:0];
-                    end
         end else begin
+            case (state)
+                S_IDLE: begin
+                    if (!rx_empty && !rx_read) begin
+                        byte_counter <= ~byte_counter;
                         rx_read <= 1'b1;
+                        dma.wdata <= {dma.wdata[7:0], rx_rdata};
+                        if (byte_counter) begin
+                            dma.request <= 1'b1;
+                            state <= S_WAIT;
+                        end
+                    end
+                end
+
+                S_WAIT: begin
+                    if (dma.ack) begin
+                        dma.address <= dma.address + 2'd2;
+                        dma.request <= 1'b0;
+                        state <= S_IDLE;
+                    end
                 end
             endcase
         end
@@ -76,10 +149,10 @@ module cpu_usb (
         .rx_read(rx_read),
         .rx_rdata(rx_rdata),
 
-        .tx_flush(tx_flush),
+        // .tx_flush(tx_flush),
-        .tx_full(tx_full),
+        // .tx_full(tx_full),
-        .tx_write(tx_write),
+        // .tx_write(tx_write),
-        .tx_wdata(tx_wdata)
+        // .tx_wdata(tx_wdata)
     );
 
 endmodule

fw/rtl/memory/memory_sdram.sv

@@ -1,8 +1,13 @@
 module memory_sdram (
     if_system sys,
-    if_n64_bus bus,
 
-    output sdram_clk,
+    input request,
+    output ack,
+    input write,
+    input [31:0] address,
+    output [15:0] rdata,
+    input [15:0] wdata,
+
     output sdram_cs,
     output sdram_ras,
     output sdram_cas,
@@ -12,25 +17,42 @@ module memory_sdram (
     inout [15:0] sdram_dq
 );
 
-    intel_gpio_ddro sdram_clk_ddro (
+    parameter [2:0] CAS_LATENCY = 3'd2;
-        .outclock(sys.sdram.sdram_clk),
-        .din({1'b0, 1'b1}),
-        .pad_out(sdram_clk)
-    );
 
-    parameter bit [2:0] CAS_LATENCY = 3'd2;
+    parameter real T_INIT       = 100_000.0;
+    parameter real T_RC         = 60.0;
+    parameter real T_RP         = 15.0;
+    parameter real T_RCD        = 15.0;
+    // parameter real T_RAS        = 37.0;          //TODO: handle this timing
+    // parameter real T_WR         = T_RAS - T_RCD; //TODO: handle this timing
+    parameter real T_MRD        = 14.0;
+    parameter real T_REF        = 7_800.0;
 
-    localparam bit [12:0] MODE_REGISTER = {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000};
+    localparam real T_CLK       = (1.0 / sc64::CLOCK_FREQUENCY) * 1_000_000_000.0;
+    localparam int C_INIT       = int'((T_INIT + T_CLK - 1) / T_CLK);
+    localparam int C_RC         = int'((T_RC + T_CLK - 1) / T_CLK);
+    localparam int C_RP         = int'((T_RP + T_CLK - 1) / T_CLK);
+    localparam int C_RCD        = int'((T_RCD + T_CLK - 1) / T_CLK);
+    // localparam int C_RAS        = int'((T_RAS + T_CLK - 1) / T_CLK);
+    // localparam int C_WR         = int'((T_WR + T_CLK - 1) / T_CLK);
+    localparam int C_MRD        = int'((T_MRD + T_CLK - 1) / T_CLK);
+    localparam int C_REF        = int'((T_REF + T_CLK - 1) / T_CLK);
+
+    localparam INIT_PRECHARGE   = C_INIT;
+    localparam INIT_REFRESH_1   = C_INIT + C_RP;
+    localparam INIT_REFRESH_2   = C_INIT + C_RP + C_RC;
+    localparam INIT_MODE_REG    = C_INIT + C_RP + (2 * C_RC);
+    localparam INIT_DONE        = C_INIT + C_RP + (2 * C_RC) + C_MRD;
 
     typedef enum bit [3:0] {
-        CMD_DESL   = 4'b1111;
+        CMD_DESL    = 4'b1111,
-        CMD_NOP    = 4'b0111;
+        CMD_NOP     = 4'b0111,
-        CMD_READ   = 4'b0101;
+        CMD_READ    = 4'b0101,
-        CMD_WRITE  = 4'b0100;
+        CMD_WRITE   = 4'b0100,
-        CMD_ACT    = 4'b0011;
+        CMD_ACT     = 4'b0011,
-        CMD_PRE    = 4'b0010;
+        CMD_PRE     = 4'b0010,
-        CMD_REF    = 4'b0001;
+        CMD_REF     = 4'b0001,
-        CMD_MRS    = 4'b0000;
+        CMD_MRS     = 4'b0000
     } e_sdram_cmd;
 
     e_sdram_cmd sdram_next_cmd;
@@ -38,29 +60,174 @@ module memory_sdram (
     logic [15:0] sdram_dq_output;
     logic sdram_dq_output_enable;
 
+    logic [14:0] current_active_bank_row;
+    logic request_in_current_active_bank_row;
+
     always_ff @(posedge sys.clk) begin
-        {o_sdram_cs, o_sdram_ras, o_sdram_cas, o_sdram_we} <= 4'(sdram_next_cmd);
+        {sdram_cs, sdram_ras, sdram_cas, sdram_we} <= 4'(sdram_next_cmd);
 
         {sdram_ba, sdram_a} <= 15'd0;
 
         sdram_dq_input <= sdram_dq;
-        sdram_dq_output <= bus.wdata;
+        sdram_dq_output <= wdata;
     
         sdram_dq_output_enable <= 1'b0;
 
         case (sdram_next_cmd)
             CMD_READ, CMD_WRITE: begin
-                {sdram_ba, sdram_a} <= {bus.address[25:24], 3'b000, bus.address[10:1]};
+                {sdram_ba, sdram_a} <= {address[25:24], 3'b000, address[10:1]};
                 sdram_dq_output_enable <= sdram_next_cmd == CMD_WRITE;
             end
-            CMD_ACT: {sdram_ba, sdram_a} <= bus.address[25:11];
+            CMD_ACT: begin
+                {sdram_ba, sdram_a} <= address[25:11];
+                current_active_bank_row <= address[25:11];
+            end
             CMD_PRE: {sdram_ba, sdram_a} <= {2'b00, 2'b00, 1'b1, 10'd0};
-            CMD_MRS: {sdram_ba, sdram_a} <= MODE_REGISTER;
+            CMD_MRS: {sdram_ba, sdram_a} <= {2'b00, 1'b0, 1'b0, 2'b00, CAS_LATENCY, 1'b0, 3'b000};
         endcase
     end
 
     always_comb begin
+        rdata = sdram_dq_input;
         sdram_dq = sdram_dq_output_enable ? sdram_dq_output : 16'hZZZZ;
+        request_in_current_active_bank_row = address[25:11] == current_active_bank_row;
+    end
+
+    typedef enum bit [2:0] {
+        S_INIT,
+        S_IDLE,
+        S_ACTIVATING,
+        S_ACTIVE,
+        S_BUSY,
+        S_PRECHARGE,
+        S_REFRESH
+    } e_state;
+
+    e_state state;
+    e_state next_state;
+
+    always_ff @(posedge sys.clk) begin
+        if (sys.reset) begin
+            state <= S_INIT;
+        end else begin
+            state <= next_state;
+        end
+    end
+
+    logic [15:0] wait_counter;
+    logic [15:0] refresh_counter;
+    logic pending_refresh;
+
+    always_ff @(posedge sys.clk) begin
+        if (sys.reset || state != next_state) begin
+            wait_counter <= 16'd0;
+        end else begin
+            wait_counter <= wait_counter + 1'd1;
+        end
+
+        if (sdram_next_cmd == CMD_REF) begin
+            refresh_counter <= 16'd0;
+        end else begin
+            refresh_counter <= refresh_counter + 1'd1;
+        end
+    end
+
+    always_comb begin
+        pending_refresh = refresh_counter >= C_REF;
+    end
+
+    logic [(CAS_LATENCY):0] read_cmd_ack_delay;
+
+    always_ff @(posedge sys.clk) begin
+        ack <= 1'b0;
+        read_cmd_ack_delay <= {sdram_next_cmd == CMD_READ, read_cmd_ack_delay[(CAS_LATENCY):1]};
+
+        if (sdram_next_cmd == CMD_WRITE || read_cmd_ack_delay[0]) begin
+            ack <= 1'b1;
+        end
+    end
+
+    always_comb begin
+        sdram_next_cmd = CMD_NOP;
+        next_state = state;
+
+        case (state)
+            S_INIT: begin
+                if (wait_counter < INIT_PRECHARGE) begin
+                    sdram_next_cmd = CMD_DESL;
+                end
+                if (wait_counter == INIT_PRECHARGE) begin
+                    sdram_next_cmd = CMD_PRE;
+                end
+                if (wait_counter == INIT_REFRESH_1 || wait_counter == INIT_REFRESH_2) begin
+                    sdram_next_cmd = CMD_REF;
+                end
+                if (wait_counter == INIT_MODE_REG) begin
+                    sdram_next_cmd = CMD_MRS;
+                end
+                if (wait_counter == INIT_DONE) begin
+                    next_state = S_IDLE;
+                end
+            end
+
+            S_IDLE: begin
+                if (pending_refresh) begin
+                    next_state = S_REFRESH;
+                    sdram_next_cmd = CMD_REF;
+                end else if (request) begin
+                    next_state = S_ACTIVATING;
+                    sdram_next_cmd = CMD_ACT;
+                end
+            end
+
+            S_ACTIVATING: begin
+                if (wait_counter == C_RCD) begin
+                    next_state = S_ACTIVE;
+                end
+            end
+
+            S_ACTIVE: begin
+                if (pending_refresh) begin
+                    next_state = S_PRECHARGE;
+                    sdram_next_cmd = CMD_PRE;
+                end else if (request) begin
+                    if (request_in_current_active_bank_row) begin
+                        next_state = S_BUSY;
+                        sdram_next_cmd = write ? CMD_WRITE : CMD_READ;
+                    end else begin
+                        next_state = S_PRECHARGE;
+                        sdram_next_cmd = CMD_PRE;
+                    end
+                end
+            end
+
+            S_BUSY: begin
+                if (ack) begin
+                    next_state <= S_ACTIVE;
+                end
+            end
+
+            S_PRECHARGE: begin
+                if (wait_counter == C_RP) begin
+                    if (pending_refresh) begin
+                        next_state = S_REFRESH;
+                        sdram_next_cmd = CMD_REF;
+                    end else begin
+                        next_state = S_IDLE;
+                    end
+                end
+            end
+
+            S_REFRESH: begin
+                if (wait_counter == C_RC) begin
+                    next_state = S_IDLE;
+                end
+            end
+
+            default: begin
+                next_state = S_IDLE;
+            end
+        endcase
     end
 
 endmodule

fw/rtl/n64/n64_pi.sv

@@ -149,7 +149,7 @@ module n64_pi (
                 n64_pi_address_valid <= 1'b1;
                 next_id <= cfg.sdram_switch ? sc64::ID_N64_SDRAM : sc64::ID_N64_BOOTLOADER;
             end
-            if (n64_pi_ad_input == 16'h1FB0) begin
+            if (n64_pi_ad_input == 16'h1FFF) begin
                 n64_pi_address_valid <= 1'b1;
                 next_id <= sc64::ID_N64_CPU;
             end
@@ -157,10 +157,11 @@ module n64_pi (
     end
 
     always_ff @(posedge sys.clk) begin
-        bus.request <= 1'b0;
+        // bus.request <= 1'b0;
 
         if (sys.reset || sys.n64_hard_reset || sys.n64_soft_reset) begin
             state <= S_IDLE;
+            bus.request <= 1'b0;
             pending_operation <= 1'b0;
         end else begin
             case (state)
@@ -187,6 +188,7 @@ module n64_pi (
                 S_WAIT: begin
                     if (bus.ack) begin
                         state <= S_IDLE;
+                        bus.request <= 1'b0;
                         n64_pi_ad_output_data_buffer <= bus.rdata;
                     end
                     if (read_op || write_op) begin
@@ -197,6 +199,7 @@ module n64_pi (
 
                 default: begin
                     state <= S_IDLE;
+                    bus.request <= 1'b0;
                     pending_operation <= 1'b0;
                 end
             endcase

fw/rtl/n64/n64_sdram.sv

@@ -0,0 +1,52 @@
+module n64_sdram (
+    if_system sys,
+    if_n64_bus bus,
+    if_dma.device dma,
+
+    output sdram_cs,
+    output sdram_ras,
+    output sdram_cas,
+    output sdram_we,
+    output [1:0] sdram_ba,
+    output [12:0] sdram_a,
+    inout [15:0] sdram_dq
+);
+
+    logic mem_request;
+    logic mem_ack;
+    logic mem_write;
+    logic [31:0] mem_address;
+    logic [15:0] mem_rdata;
+    logic [15:0] mem_wdata;
+
+    always_comb begin
+        mem_request = bus.request || dma.request;
+        bus.ack = bus.request && mem_ack;
+        dma.ack = dma.request && mem_ack;
+        mem_write = (bus.request && bus.write) || (dma.request && dma.write);
+        mem_address = dma.request ? dma.address : bus.address;
+        mem_wdata = dma.request ? dma.wdata : bus.wdata;
+        bus.rdata = mem_rdata;
+        dma.rdata = mem_rdata;
+    end
+
+    memory_sdram memory_sdram_inst (
+        .sys(sys),
+
+        .request(mem_request),
+        .ack(mem_ack),
+        .write(mem_write),
+        .address(mem_address),
+        .rdata(mem_rdata),
+        .wdata(mem_wdata),
+
+        .sdram_cs(sdram_cs),
+        .sdram_ras(sdram_ras),
+        .sdram_cas(sdram_cas),
+        .sdram_we(sdram_we),
+        .sdram_ba(sdram_ba),
+        .sdram_a(sdram_a),
+        .sdram_dq(sdram_dq)
+    );
+
+endmodule

fw/rtl/n64/n64_soc.sv

@@ -1,6 +1,7 @@
 module n64_soc (
     if_system sys,
     if_config cfg,
+    if_dma.device dma,
 
     input n64_pi_alel,
     input n64_pi_aleh,
@@ -11,7 +12,6 @@ module n64_soc (
     input n64_si_clk,
     inout n64_si_dq,
 
-    output sdram_clk,
     output sdram_cs,
     output sdram_ras,
     output sdram_cas,
@@ -35,11 +35,11 @@ module n64_soc (
         .n64_pi_ad(n64_pi_ad)
     );
 
-    memory_sdram memory_sdram_inst (
+    n64_sdram n64_sdram_inst (
         .sys(sys),
         .bus(bus.at[sc64::ID_N64_SDRAM].device),
+        .dma(dma),
 
-        .sdram_clk(sdram_clk),
         .sdram_cs(sdram_cs),
         .sdram_ras(sdram_ras),
         .sdram_cas(sdram_cas),

fw/rtl/system/config.sv

@@ -10,7 +10,7 @@ interface if_config ();
     logic [25:0] save_offset;
 
     always_comb begin
-        sdram_switch = 1'b0;
+        sdram_switch = 1'b1;
         sdram_writable = 1'b0;
         dd_enabled = 1'b1;
         sram_enabled = 1'b1;

fw/rtl/system/sc64.sv

@@ -19,6 +19,8 @@ package sc64;
         __ID_CPU_END
     } e_cpu_id;
 
+    parameter CLOCK_FREQUENCY   = 100_000_000;
+
     parameter UART_BAUD_RATE    = 1_000_000;
 
 endpackage

fw/rtl/system/system.sv

@@ -49,10 +49,10 @@ module system (if_system.internal sys);
         .locked(locked)
     );
 
-    intel_snp intel_snp_inst (
+    // intel_snp intel_snp_inst (
-        .source(external_reset),
+    //     .source(external_reset),
-        .source_clk(sys.clk)
+    //     .source_clk(sys.clk)
-    );
+    // );
 
     always_ff @(posedge sys.clk) begin
         n64_reset_ff <= {n64_reset_ff[0], sys.n64_reset};