mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-21 21:49:15 +01:00
bscript updated
This commit is contained in:
Polprzewodnikowy
parent
8485face13
commit
55f46e5dda
2
.github/workflows/main.yml
vendored
2
.github/workflows/main.yml
vendored
@ -22,7 +22,7 @@ jobs:
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submodules: true
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- name: Build script
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run: ./docker_build.sh release
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run: ./docker_build.sh release --force-clean
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- name: Upload artifact
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uses: actions/upload-artifact@v2
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2
.gitmodules
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2
.gitmodules
vendored
@ -1,4 +1,4 @@
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[submodule "fw/cpu/picorv32"]
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[submodule "fw/picorv32"]
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path = fw/picorv32
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url = https://github.com/cliffordwolf/picorv32.git
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ignore = dirty
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46
build.sh
46
build.sh
@ -19,6 +19,9 @@ BUILT_FPGA=false
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BUILT_UPDATE=false
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BUILT_RELEASE=false
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FORCE_CLEAN=false
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SKIP_FPGA_REBUILD=false
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build_cic () {
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if [ "$BUILT_CIC" = true ]; then return; fi
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@ -33,7 +36,10 @@ build_n64 () {
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if [ "$BUILT_N64" = true ]; then return; fi
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pushd sw/n64
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make clean all
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if [ "$FORCE_CLEAN" = true ]; then
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make clean
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fi
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make all
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popd
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BUILT_N64=true
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@ -43,7 +49,10 @@ build_riscv () {
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if [ "$BUILT_RISCV" = true ]; then return; fi
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pushd sw/riscv
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make clean all
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if [ "$FORCE_CLEAN" = true ]; then
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make clean
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fi
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make all
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popd
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BUILT_RISCV=true
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@ -56,7 +65,12 @@ build_fpga () {
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build_riscv
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pushd fw
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quartus_sh --flow compile ./SummerCart64.qpf
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if [ "$SKIP_FPGA_REBUILD" = true ] && [ -f output_files/SummerCart64.done ]; then
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quartus_asm SummerCart64
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quartus_cpf -c SummerCart64.cof
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else
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quartus_sh --flow compile ./SummerCart64.qpf
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fi
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popd
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BUILT_FPGA=true
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@ -92,15 +106,19 @@ build_release () {
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print_usage () {
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echo "builder script for SummerCart64"
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echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [--help]"
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echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [-c] [-s] [--help]"
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echo "parameters:"
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echo " cic - assemble UltraCIC-III software"
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echo " n64 - compile N64 bootloader software"
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echo " riscv - compile cart governor software"
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echo " fpga - compile FPGA design (triggers 'n64' and 'riscv' build)"
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echo " update - convert programming .pof file to raw binary for user upgrade (triggers 'fpga' build)"
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echo " release - collect and zip files for release (triggers 'cic' and 'update' build)"
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echo " --help - print this guide"
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echo " cic - assemble UltraCIC-III software"
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echo " n64 - compile N64 bootloader software"
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echo " riscv - compile cart governor software"
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echo " fpga - compile FPGA design (triggers 'n64' and 'riscv' build)"
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echo " update - convert programming .pof file to raw binary for self-upgrade (triggers 'fpga' build)"
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echo " release - collect and zip files for release (triggers 'cic' and 'update' build)"
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echo " -c | --force-clean"
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echo " - clean software compilation result directories before build"
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echo " -s | --skip-fpga-rebuild"
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echo " - do not recompile whole FPGA design if it's already done, just update software binaries"
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echo " --help - print this guide"
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}
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if test $# -eq 0; then
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@ -137,6 +155,12 @@ while test $# -gt 0; do
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release)
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TRIGGER_RELEASE=true
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;;
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-c|--force-clean)
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FORCE_CLEAN=true
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;;
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-s|--skip-fpga-rebuild)
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SKIP_FPGA_REBUILD=true
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;;
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--help)
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print_usage
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exit 0
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@ -19,7 +19,7 @@
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#
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# Quartus Prime
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# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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# Date created = 23:52:20 November 09, 2021
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# Date created = 13:29:40 November 11, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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@ -83,7 +83,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
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set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:scripts/post_flow.tcl"
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set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl"
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# Pin & Location Assignments
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# ==========================
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@ -289,22 +289,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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# -------------------------
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# end ENTITY(SummerCart64)
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# ------------------------
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# ------------------------------
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# start ENTITY(altera_gpio_lite)
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# Project-Wide Assignments
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# ========================
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# end ENTITY(altera_gpio_lite)
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# ----------------------------
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# -----------------------------
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# start ENTITY(intel_gpio_ddro)
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# Project-Wide Assignments
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# ========================
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# end ENTITY(intel_gpio_ddro)
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# ---------------------------
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# ------------------------
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@ -1,6 +1,6 @@
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set flow [lindex $quartus(args) 0]
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if [string match "compile" $flow] {
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if [string match "quartus_asm" $flow] {
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post_message "Generating final programming file"
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qexec "quartus_cpf -c SummerCart64.cof"
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}
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