The-Homebrew-Cloud/SummerCart64
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bug fix

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Polprzewodnikowy 2021-03-01 00:42:48 +01:00
parent 88854ed0e9
commit 790f30ae20
3 changed files with 7 additions and 8 deletions
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3
README.md
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@ -55,8 +55,7 @@ Instructions below are mostly written for Windows users and point to Windows spe
There are several issues with the project at the moment in order of importance. Keep in mind that core flashcart functionality is fully working: There are several issues with the project at the moment in order of importance. Keep in mind that core flashcart functionality is fully working:
- No FlashRAM save emulation implementation. - No save write-back to SD card without console reset implementation.
- No save write-back to SD card implementation.
- No RTC implementation. - No RTC implementation.

2
fw/SummerCart64.qsf
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@ -19,7 +19,7 @@
# #
# Quartus Prime # Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 15:52:44 February 27, 2021 # Date created = 00:41:07 March 01, 2021
# #
# -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- #
# #

10
fw/rtl/flashram/flashram_controller.v
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@ -217,16 +217,16 @@ module flashram_controller (
reg [15:0] r_items_left; reg [15:0] r_items_left;
wire w_execute_done = !r_execute_start && (r_items_left == 16'd0) && r_flashram_state[STATE_EXECUTE]; wire w_in_execution = !r_execute_start && r_flashram_state[STATE_EXECUTE];
wire w_read_phase_done = w_execute_done && !o_mem_write && i_mem_ack; wire w_read_phase_done = w_in_execution && (r_write_buffer_address == 5'h1F) && !o_mem_write && i_mem_ack;
wire w_write_phase_done = w_execute_done && o_mem_write; wire w_write_phase_done = w_in_execution && (r_items_left == 16'd0) && o_mem_write;
wire w_mem_request_successful = o_mem_request && !i_mem_busy; wire w_mem_request_successful = o_mem_request && !i_mem_busy;
wire w_address_reset = r_execute_start || w_read_phase_done; wire w_address_reset = r_execute_start || w_read_phase_done;
wire w_write_buffer_address_increment = o_mem_write ? w_mem_request_successful : i_mem_ack; wire w_write_buffer_address_increment = o_mem_write ? w_mem_request_successful : i_mem_ack;
always @(posedge i_clk) begin always @(*) begin
r_execute_done <= w_write_phase_done; r_execute_done = w_write_phase_done;
end end
always @(posedge i_clk) begin always @(posedge i_clk) begin