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bug fix
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@ -55,8 +55,7 @@ Instructions below are mostly written for Windows users and point to Windows spe
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There are several issues with the project at the moment in order of importance. Keep in mind that core flashcart functionality is fully working:
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- No FlashRAM save emulation implementation.
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- No save write-back to SD card implementation.
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- No save write-back to SD card without console reset implementation.
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- No RTC implementation.
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@ -19,7 +19,7 @@
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#
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# Quartus Prime
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# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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# Date created = 15:52:44 February 27, 2021
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# Date created = 00:41:07 March 01, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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@ -217,16 +217,16 @@ module flashram_controller (
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reg [15:0] r_items_left;
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wire w_execute_done = !r_execute_start && (r_items_left == 16'd0) && r_flashram_state[STATE_EXECUTE];
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wire w_read_phase_done = w_execute_done && !o_mem_write && i_mem_ack;
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wire w_write_phase_done = w_execute_done && o_mem_write;
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wire w_in_execution = !r_execute_start && r_flashram_state[STATE_EXECUTE];
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wire w_read_phase_done = w_in_execution && (r_write_buffer_address == 5'h1F) && !o_mem_write && i_mem_ack;
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wire w_write_phase_done = w_in_execution && (r_items_left == 16'd0) && o_mem_write;
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wire w_mem_request_successful = o_mem_request && !i_mem_busy;
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wire w_address_reset = r_execute_start || w_read_phase_done;
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wire w_write_buffer_address_increment = o_mem_write ? w_mem_request_successful : i_mem_ack;
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always @(posedge i_clk) begin
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r_execute_done <= w_write_phase_done;
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always @(*) begin
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r_execute_done = w_write_phase_done;
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end
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always @(posedge i_clk) begin
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