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Polprzewodnikowy 2021-08-29 19:52:41 +02:00
parent 8a2a729a69
commit 975a98c03e
1 changed files with 2 additions and 2 deletions
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4
fw/rtl/cpu/cpu_wrapper.sv
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@ -10,8 +10,8 @@ module cpu_wrapper (
e_bus_state state;
logic mem_la_read;
logic mem_la_write;
logic mem_la_read;
logic mem_la_write;
always_ff @(posedge sys.clk) begin
bus.request <= 1'b0;