mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-24 12:01:56 +01:00
pre usb disaster
This commit is contained in:
Polprzewodnikowy
parent
90b211c179
commit
97b7291001
@ -48,7 +48,8 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys
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set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
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set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
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# set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
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set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip
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set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
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set_global_assignment -name SDC_FILE SummerCart64.sdc
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set_global_assignment -name SIGNALTAP_FILE stp.stp
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@ -301,4 +302,4 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# ------------------------
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set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip
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set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -2,11 +2,11 @@
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derive_pll_clocks -create_base_clocks
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# set sys_clk {sys_pll|altpll_component|auto_generated|pll1|clk[0]}
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# set sdram_pll_clk {sys_pll|altpll_component|auto_generated|pll1|clk[1]}
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set sys_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]}
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set sdram_pll_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]}
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# set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q}
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create_generated_clock -name sdram_clk -source [get_pins {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {o_sdram_clk}]
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create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}]
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# create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
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# create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
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@ -18,7 +18,7 @@ create_generated_clock -name flash_se_neg_reg \
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derive_clock_uncertainty
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# # SDRAM timings
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# SDRAM timings
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set sdram_outputs {o_sdram_cs o_sdram_ras o_sdram_cas o_sdram_we o_sdram_a[*] o_sdram_ba[*] io_sdram_dq[*]}
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set sdram_inputs {io_sdram_dq[*]}
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@ -29,16 +29,10 @@ set_output_delay -clock [get_clocks {sdram_clk}] -min -0.8 [get_ports $sdram_out
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set_input_delay -clock [get_clocks {sdram_clk}] -max 5.4 [get_ports $sdram_inputs]
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set_input_delay -clock [get_clocks {sdram_clk}] -min 2.5 [get_ports $sdram_inputs]
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set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]
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set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk]
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# # FTDI timings
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# set_false_path -to [get_ports {o_ftdi_clk o_ftdi_si}]
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# set_false_path -from [get_ports {i_ftdi_so i_ftdi_cts}]
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# # SD card timings
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# SD card timings
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# set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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# set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
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@ -57,6 +51,7 @@ set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks
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set_false_path -to [get_ports {o_usb_clk io_usb_miosi[*] o_usb_cs}]
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set_false_path -from [get_ports {io_usb_miosi[*] i_usb_miso}]
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# N64, PI and SI timings
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set_false_path -to [get_ports {o_n64_irq}]
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@ -88,5 +83,5 @@ set_false_path -from [get_ports {io_rtc_sda}]
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# JTAG timings
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set_false_path -to [get_ports {altera_reserved_tdo}]
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set_false_path -from [get_ports {altera_reserved_tdi altera_reserved_tms}]
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# set_false_path -to [get_ports {altera_reserved_tdo}]
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# set_false_path -from [get_ports {altera_reserved_tdi altera_reserved_tms}]
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4
fw/rtl/intel/fifo/intel_fifo_8.qip
Normal file
4
fw/rtl/intel/fifo/intel_fifo_8.qip
Normal file
@ -0,0 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "FIFO"
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set_global_assignment -name IP_TOOL_VERSION "20.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_fifo_8.v"]
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163
fw/rtl/intel/fifo/intel_fifo_8.v
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163
fw/rtl/intel/fifo/intel_fifo_8.v
Normal file
@ -0,0 +1,163 @@
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: scfifo
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// ============================================================
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// File Name: intel_fifo_8.v
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// Megafunction Name(s):
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// scfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2020 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and any partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details, at
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//https://fpgasoftware.intel.com/eula.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module intel_fifo_8 (
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clock,
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data,
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rdreq,
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sclr,
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wrreq,
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empty,
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full,
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q);
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input clock;
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input [7:0] data;
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input rdreq;
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input sclr;
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input wrreq;
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output empty;
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output full;
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output [7:0] q;
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wire sub_wire0;
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wire sub_wire1;
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wire [7:0] sub_wire2;
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wire empty = sub_wire0;
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wire full = sub_wire1;
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wire [7:0] q = sub_wire2[7:0];
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scfifo scfifo_component (
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.clock (clock),
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.data (data),
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.rdreq (rdreq),
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.sclr (sclr),
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.wrreq (wrreq),
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.empty (sub_wire0),
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.full (sub_wire1),
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.q (sub_wire2),
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.aclr (),
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.almost_empty (),
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.almost_full (),
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.eccstatus (),
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.usedw ());
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defparam
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scfifo_component.add_ram_output_register = "ON",
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scfifo_component.intended_device_family = "MAX 10",
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scfifo_component.lpm_numwords = 1024,
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scfifo_component.lpm_showahead = "ON",
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scfifo_component.lpm_type = "scfifo",
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scfifo_component.lpm_width = 8,
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scfifo_component.lpm_widthu = 10,
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scfifo_component.overflow_checking = "ON",
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scfifo_component.underflow_checking = "ON",
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scfifo_component.use_eab = "ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Depth NUMERIC "1024"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "1"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: UsedW NUMERIC "0"
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// Retrieval info: PRIVATE: Width NUMERIC "8"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "8"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -35,7 +35,7 @@ module memory_flash (
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e_state state;
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always_ff @(posedge sys.clk) begin
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dummy_ack <= 1'b1;
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dummy_ack <= 1'b0;
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if (sys.reset) begin
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state <= S_IDLE;
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@ -19,14 +19,51 @@ module n64_sdram (
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logic [15:0] mem_rdata;
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logic [15:0] mem_wdata;
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typedef enum bit [0:0] {
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S_IDLE,
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S_WAIT
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} e_state;
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typedef enum bit [0:0] {
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T_BUS,
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T_DMA
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} e_bus_or_dma;
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e_state state;
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e_bus_or_dma bus_or_dma;
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always_ff @(posedge sys.clk) begin
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if (sys.reset) begin
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state <= S_IDLE;
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mem_request <= 1'b0;
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end else begin
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case (state)
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S_IDLE: begin
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if (bus.request || dma.request) begin
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state <= S_WAIT;
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mem_request <= 1'b1;
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mem_write <= bus.request ? bus.write : dma.write;
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mem_address <= bus.request ? bus.address : dma.address;
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mem_wdata <= bus.request ? bus.wdata : dma.wdata;
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bus_or_dma <= bus.request ? T_BUS : T_DMA;
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end
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end
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S_WAIT: begin
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if (mem_ack) begin
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state <= S_IDLE;
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mem_request <= 1'b0;
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end
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end
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endcase
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end
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end
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always_comb begin
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mem_request = bus.request || dma.request;
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bus.ack = bus.request && mem_ack;
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dma.ack = dma.request && mem_ack;
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mem_write = (bus.request && bus.write) || (dma.request && dma.write);
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mem_address = dma.request ? dma.address : bus.address;
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mem_wdata = dma.request ? dma.wdata : bus.wdata;
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bus.ack = bus_or_dma == T_BUS && mem_ack;
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bus.rdata = mem_rdata;
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dma.ack = bus_or_dma == T_DMA && mem_ack;
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dma.rdata = mem_rdata;
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end
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@ -9,13 +9,13 @@ module usb_ft1248 (
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input rx_flush,
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output rx_empty,
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output rx_almost_empty,
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// output rx_almost_empty,
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input rx_read,
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output [7:0] rx_rdata,
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input tx_flush,
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output tx_full,
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output tx_almost_full,
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// output tx_almost_full,
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input tx_write,
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input [7:0] tx_wdata
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);
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@ -31,22 +31,22 @@ module usb_ft1248 (
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reg tx_read;
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wire [7:0] tx_rdata;
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fifo8 fifo_8_rx_inst (
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intel_fifo_8 fifo_8_rx_inst (
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.clock(sys.clk),
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.sclr(rx_flush),
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.empty(rx_empty),
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.almost_empty(rx_almost_empty),
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// .almost_empty(rx_almost_empty),
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.rdreq(rx_read),
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.q(rx_rdata),
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.full(rx_full),
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.almost_full(rx_almost_full),
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// .almost_full(rx_almost_full),
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.wrreq(rx_write),
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.data(rx_wdata)
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);
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fifo8 fifo_8_tx_inst (
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intel_fifo_8 fifo_8_tx_inst (
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.clock(sys.clk),
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.sclr(tx_flush),
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@ -55,7 +55,7 @@ module usb_ft1248 (
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.q(tx_rdata),
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.full(tx_full),
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.almost_full(tx_almost_full),
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// .almost_full(tx_almost_full),
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.wrreq(tx_write),
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.data(tx_wdata)
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);
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608
fw/stp.stp
608
fw/stp.stp
File diff suppressed because one or more lines are too long
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