pre usb disaster

fw/SummerCart64.qsf

@@ -48,7 +48,8 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
 set_global_assignment -name QSYS_FILE rtl/intel/flash/intel_flash.qsys
 set_global_assignment -name QSYS_FILE rtl/intel/snp/intel_snp.qsys
-set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
+# set_global_assignment -name QIP_FILE rtl/intel/fifo/fifo8.qip
+set_global_assignment -name QIP_FILE rtl/intel/fifo/intel_fifo_8.qip
 set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
 set_global_assignment -name SDC_FILE SummerCart64.sdc
 set_global_assignment -name SIGNALTAP_FILE stp.stp

fw/SummerCart64.sdc

@@ -2,11 +2,11 @@
 
 derive_pll_clocks -create_base_clocks
 
-# set sys_clk {sys_pll|altpll_component|auto_generated|pll1|clk[0]}
+set sys_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]}
-# set sdram_pll_clk {sys_pll|altpll_component|auto_generated|pll1|clk[1]}
+set sdram_pll_clk {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]}
 # set sd_reg_clk {sd_interface_inst|sd_clk_inst|o_sd_clk|q}
 
-create_generated_clock -name sdram_clk -source [get_pins {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {o_sdram_clk}]
+create_generated_clock -name sdram_clk -source [get_pins $sdram_pll_clk] [get_ports {o_sdram_clk}]
 # create_generated_clock -name sd_reg_clk -source [get_pins {sd_interface_inst|sd_clk_inst|o_sd_clk|clk}] -divide_by 2 [get_pins $sd_reg_clk]
 # create_generated_clock -name sd_clk -source [get_pins $sd_reg_clk] [get_ports {o_sd_clk}]
 
@@ -18,7 +18,7 @@ create_generated_clock -name flash_se_neg_reg \
 derive_clock_uncertainty
 
 
-# # SDRAM timings
+# SDRAM timings
 
 set sdram_outputs {o_sdram_cs o_sdram_ras o_sdram_cas o_sdram_we o_sdram_a[*] o_sdram_ba[*] io_sdram_dq[*]}
 set sdram_inputs {io_sdram_dq[*]}
@@ -29,16 +29,10 @@ set_output_delay -clock [get_clocks {sdram_clk}] -min -0.8 [get_ports $sdram_out
 set_input_delay -clock [get_clocks {sdram_clk}] -max 5.4 [get_ports $sdram_inputs]
 set_input_delay -clock [get_clocks {sdram_clk}] -min 2.5 [get_ports $sdram_inputs]
 
-set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks {system_inst|intel_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]
+set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks $sys_clk]
 
 
-# # FTDI timings
+# SD card timings
-
-# set_false_path -to [get_ports {o_ftdi_clk o_ftdi_si}]
-# set_false_path -from [get_ports {i_ftdi_so i_ftdi_cts}]
-
-
-# # SD card timings
 
 # set_output_delay -clock [get_clocks {sd_clk}] -max 6.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
 # set_output_delay -clock [get_clocks {sd_clk}] -min -2.0 [get_ports {io_sd_cmd io_sd_dat[*]}]
@@ -57,6 +51,7 @@ set_multicycle_path -setup -end 2 -from [get_clocks {sdram_clk}] -to [get_clocks
 set_false_path -to [get_ports {o_usb_clk io_usb_miosi[*] o_usb_cs}]
 set_false_path -from [get_ports {io_usb_miosi[*] i_usb_miso}]
 
+
 # N64, PI and SI timings
 
 set_false_path -to [get_ports {o_n64_irq}]
@@ -88,5 +83,5 @@ set_false_path -from [get_ports {io_rtc_sda}]
 
 # JTAG timings
 
-set_false_path -to [get_ports {altera_reserved_tdo}]
+# set_false_path -to [get_ports {altera_reserved_tdo}]
-set_false_path -from [get_ports {altera_reserved_tdi altera_reserved_tms}]
+# set_false_path -from [get_ports {altera_reserved_tdi altera_reserved_tms}]

fw/rtl/intel/fifo/intel_fifo_8.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "intel_fifo_8.v"]

fw/rtl/intel/fifo/intel_fifo_8.v

@@ -0,0 +1,163 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: intel_fifo_8.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module intel_fifo_8 (
+	clock,
+	data,
+	rdreq,
+	sclr,
+	wrreq,
+	empty,
+	full,
+	q);
+
+	input	  clock;
+	input	[7:0]  data;
+	input	  rdreq;
+	input	  sclr;
+	input	  wrreq;
+	output	  empty;
+	output	  full;
+	output	[7:0]  q;
+
+	wire  sub_wire0;
+	wire  sub_wire1;
+	wire [7:0] sub_wire2;
+	wire  empty = sub_wire0;
+	wire  full = sub_wire1;
+	wire [7:0] q = sub_wire2[7:0];
+
+	scfifo	scfifo_component (
+				.clock (clock),
+				.data (data),
+				.rdreq (rdreq),
+				.sclr (sclr),
+				.wrreq (wrreq),
+				.empty (sub_wire0),
+				.full (sub_wire1),
+				.q (sub_wire2),
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.eccstatus (),
+				.usedw ());
+	defparam
+		scfifo_component.add_ram_output_register = "ON",
+		scfifo_component.intended_device_family = "MAX 10",
+		scfifo_component.lpm_numwords = 1024,
+		scfifo_component.lpm_showahead = "ON",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 8,
+		scfifo_component.lpm_widthu = 10,
+		scfifo_component.overflow_checking = "ON",
+		scfifo_component.underflow_checking = "ON",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL intel_fifo_8_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf

fw/rtl/memory/memory_flash.sv

@@ -35,7 +35,7 @@ module memory_flash (
     e_state state;
 
     always_ff @(posedge sys.clk) begin
-        dummy_ack <= 1'b1;
+        dummy_ack <= 1'b0;
 
         if (sys.reset) begin
             state <= S_IDLE;

fw/rtl/n64/n64_sdram.sv

@@ -19,14 +19,51 @@ module n64_sdram (
     logic [15:0] mem_rdata;
     logic [15:0] mem_wdata;
 
+    typedef enum bit [0:0] { 
+        S_IDLE,
+        S_WAIT
+    } e_state;
+
+    typedef enum bit [0:0] { 
+        T_BUS,
+        T_DMA
+    } e_bus_or_dma;
+
+    e_state state;
+    e_bus_or_dma bus_or_dma;
+
+    always_ff @(posedge sys.clk) begin
+        if (sys.reset) begin
+            state <= S_IDLE;
+            mem_request <= 1'b0;
+        end else begin
+            case (state)
+                S_IDLE: begin
+                    if (bus.request || dma.request) begin
+                        state <= S_WAIT;
+                        mem_request <= 1'b1;
+                        mem_write <= bus.request ? bus.write : dma.write;
+                        mem_address <= bus.request ? bus.address : dma.address;
+                        mem_wdata <= bus.request ? bus.wdata : dma.wdata;
+                        bus_or_dma <= bus.request ? T_BUS : T_DMA;
+                    end
+                end
+
+                S_WAIT: begin
+                    if (mem_ack) begin
+                        state <= S_IDLE;
+                        mem_request <= 1'b0;
+                    end
+                end
+            endcase
+        end
+    end
+
     always_comb begin
-        mem_request = bus.request || dma.request;
+        bus.ack = bus_or_dma == T_BUS && mem_ack;
-        bus.ack = bus.request && mem_ack;
-        dma.ack = dma.request && mem_ack;
-        mem_write = (bus.request && bus.write) || (dma.request && dma.write);
-        mem_address = dma.request ? dma.address : bus.address;
-        mem_wdata = dma.request ? dma.wdata : bus.wdata;
         bus.rdata = mem_rdata;
+
+        dma.ack = bus_or_dma == T_DMA && mem_ack;
         dma.rdata = mem_rdata;
     end
 

fw/rtl/usb/usb_ft1248.sv

@@ -9,13 +9,13 @@ module usb_ft1248 (
 
     input rx_flush,
     output rx_empty,
-    output rx_almost_empty,
+    // output rx_almost_empty,
     input rx_read,
     output [7:0] rx_rdata,
 
     input tx_flush,
     output tx_full,
-    output tx_almost_full,
+    // output tx_almost_full,
     input tx_write,
     input [7:0] tx_wdata
 );
@@ -31,22 +31,22 @@ module usb_ft1248 (
     reg tx_read;
     wire [7:0] tx_rdata;
 
-    fifo8 fifo_8_rx_inst (
+    intel_fifo_8 fifo_8_rx_inst (
         .clock(sys.clk),
         .sclr(rx_flush),
 
         .empty(rx_empty),
-        .almost_empty(rx_almost_empty),
+        // .almost_empty(rx_almost_empty),
         .rdreq(rx_read),
         .q(rx_rdata),
 
         .full(rx_full),
-        .almost_full(rx_almost_full),
+        // .almost_full(rx_almost_full),
         .wrreq(rx_write),
         .data(rx_wdata)
     );
 
-    fifo8 fifo_8_tx_inst (
+    intel_fifo_8 fifo_8_tx_inst (
         .clock(sys.clk),
         .sclr(tx_flush),
 
@@ -55,7 +55,7 @@ module usb_ft1248 (
         .q(tx_rdata),
 
         .full(tx_full),
-        .almost_full(tx_almost_full),
+        // .almost_full(tx_almost_full),
         .wrreq(tx_write),
         .data(tx_wdata)
     );