The-Homebrew-Cloud/SummerCart64
2
0
Fork 0
mirror of https://github.com/Polprzewodnikowy/SummerCart64.git synced 2024-11-22 05:59:15 +01:00
Code Issues Packages Projects Releases Wiki Activity

small cleanup

Browse Source
This commit is contained in:
Mateusz Faderewski 2024-07-07 14:42:39 +02:00
parent b284bb9f06
commit e89529275a
3 changed files with 18 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fw/rtl/memory/memory_sdram.sv
View File

@ -95,7 +95,7 @@ module memory_sdram (
CMD_MRS: begin
{sdram_ba, sdram_a} <= {
2'b00, // [BA1:BA0] Reserved = 0
3'b00, // [A12:A10] Reserved = 0
3'b000, // [A12:A10] Reserved = 0
1'b0, // [A9] Write Burst Mode = Programmed Burst Length
2'b00, // [A8:A7] Operating Mode = Standard Operation
CAS_LATENCY, // [A6:A4] Latency Mode = 2

1
fw/tests/mocks/fifo_bus_mock.sv
View File

@ -16,6 +16,7 @@ module fifo_bus_mock #(
localparam int PTR_BITS = $clog2(DEPTH);
// RX FIFO mock
logic [7:0] rx_fifo_mem [0:(DEPTH - 1)];

32
fw/tests/mocks/memory_sdram_mock.sv
View File

@ -37,26 +37,26 @@ module memory_sdram_mock (
assign sdram_dq = sdram_dq_driven;
initial begin
cas_delay = 2'b00;
data_from_sdram = 16'h0102;
data_to_sdram = 16'hFFFF;
end
always_ff @(posedge clk) begin
cas_delay <= {cas_delay[0], 1'b0};
if (reset) begin
cas_delay <= 2'b00;
data_from_sdram <= 16'h0102;
data_to_sdram <= 16'hFFFF;
end else begin
cas_delay <= {cas_delay[0], 1'b0};
if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
cas_delay[0] <= 1'b1;
end
if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
cas_delay[0] <= 1'b1;
end
if (cas_delay[1]) begin
data_from_sdram <= data_from_sdram + 16'h0202;
end
if (cas_delay[1]) begin
data_from_sdram <= data_from_sdram + 16'h0202;
end
if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0100) begin
if (!sdram_dqm[0]) data_to_sdram[7:0] <= sdram_dq[7:0];
if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0100) begin
if (!sdram_dqm[0]) data_to_sdram[7:0] <= sdram_dq[7:0];
if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
end
end
end