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https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2025-02-19 21:42:42 +01:00
small cleanup
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b284bb9f06
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@ -95,7 +95,7 @@ module memory_sdram (
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CMD_MRS: begin
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CMD_MRS: begin
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{sdram_ba, sdram_a} <= {
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{sdram_ba, sdram_a} <= {
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2'b00, // [BA1:BA0] Reserved = 0
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2'b00, // [BA1:BA0] Reserved = 0
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3'b00, // [A12:A10] Reserved = 0
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3'b000, // [A12:A10] Reserved = 0
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1'b0, // [A9] Write Burst Mode = Programmed Burst Length
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1'b0, // [A9] Write Burst Mode = Programmed Burst Length
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2'b00, // [A8:A7] Operating Mode = Standard Operation
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2'b00, // [A8:A7] Operating Mode = Standard Operation
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CAS_LATENCY, // [A6:A4] Latency Mode = 2
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CAS_LATENCY, // [A6:A4] Latency Mode = 2
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@ -16,6 +16,7 @@ module fifo_bus_mock #(
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localparam int PTR_BITS = $clog2(DEPTH);
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localparam int PTR_BITS = $clog2(DEPTH);
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// RX FIFO mock
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// RX FIFO mock
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logic [7:0] rx_fifo_mem [0:(DEPTH - 1)];
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logic [7:0] rx_fifo_mem [0:(DEPTH - 1)];
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@ -37,13 +37,12 @@ module memory_sdram_mock (
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assign sdram_dq = sdram_dq_driven;
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assign sdram_dq = sdram_dq_driven;
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initial begin
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cas_delay = 2'b00;
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data_from_sdram = 16'h0102;
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data_to_sdram = 16'hFFFF;
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end
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (reset) begin
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cas_delay <= 2'b00;
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data_from_sdram <= 16'h0102;
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data_to_sdram <= 16'hFFFF;
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end else begin
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cas_delay <= {cas_delay[0], 1'b0};
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cas_delay <= {cas_delay[0], 1'b0};
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if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
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if ({sdram_cs, sdram_ras, sdram_cas, sdram_we} == 4'b0101) begin
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@ -59,6 +58,7 @@ module memory_sdram_mock (
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if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
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if (!sdram_dqm[1]) data_to_sdram[15:8] <= sdram_dq[15:8];
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end
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end
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end
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end
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end
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always_comb begin
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always_comb begin
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sdram_dq_driven = 16'hXXXX;
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sdram_dq_driven = 16'hXXXX;
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