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PI address debug

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This commit is contained in:
Mateusz Faderewski 2022-11-05 22:54:52 +01:00
parent 5e7959cb95
commit f5652a0108
6 changed files with 36 additions and 16 deletions
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11
fw/rtl/mcu/mcu_top.sv
View File

@ -356,7 +356,8 @@ module mcu_top (
REG_DD_DRIVE_ID, REG_DD_DRIVE_ID,
REG_VENDOR_SCR, REG_VENDOR_SCR,
REG_VENDOR_DATA, REG_VENDOR_DATA,
REG_DEBUG REG_DEBUG_0,
REG_DEBUG_1
} reg_address_e; } reg_address_e;
logic bootloader_skip; logic bootloader_skip;
@ -631,10 +632,14 @@ module mcu_top (
reg_rdata <= vendor_scb.data_rdata; reg_rdata <= vendor_scb.data_rdata;
end end
REG_DEBUG: begin REG_DEBUG_0: begin
reg_rdata <= n64_scb.pi_debug[31:0];
end
REG_DEBUG_1: begin
reg_rdata <= { reg_rdata <= {
28'd0, 28'd0,
n64_scb.pi_debug n64_scb.pi_debug[35:32]
}; };
end end
endcase endcase

28
fw/rtl/n64/n64_pi.sv
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@ -122,6 +122,18 @@ module n64_pi (
end end
// Debug: last accessed PI address
always_ff @(posedge clk) begin
if (aleh_op) begin
n64_scb.pi_debug[31:16] <= n64_pi_dq_in;
end
if (alel_op) begin
n64_scb.pi_debug[15:0] <= n64_pi_dq_in;
end
end
// Address decoding // Address decoding
const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000; const bit [31:0] DDIPL_OFFSET = 32'h03BC_0000;
@ -289,8 +301,8 @@ module n64_pi (
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
read_fifo_read <= 1'b0; read_fifo_read <= 1'b0;
if (reset) begin if (!pi_reset) begin
n64_scb.pi_debug[1:0] <= 2'b00; n64_scb.pi_debug[33:32] <= 2'b00;
end end
if (reset || !pi_reset || alel_op) begin if (reset || !pi_reset || alel_op) begin
@ -301,9 +313,9 @@ module n64_pi (
if (read_op) begin if (read_op) begin
if (read_fifo_empty) begin if (read_fifo_empty) begin
read_fifo_wait <= 1'b1; read_fifo_wait <= 1'b1;
n64_scb.pi_debug[0] <= 1'b1; n64_scb.pi_debug[32] <= 1'b1;
if (read_fifo_wait) begin if (read_fifo_wait) begin
n64_scb.pi_debug[1] <= 1'b1; n64_scb.pi_debug[33] <= 1'b1;
end end
end else begin end else begin
read_fifo_read <= 1'b1; read_fifo_read <= 1'b1;
@ -356,8 +368,8 @@ module n64_pi (
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
write_fifo_write <= 1'b0; write_fifo_write <= 1'b0;
if (reset) begin if (!pi_reset) begin
n64_scb.pi_debug[3:2] <= 2'b00; n64_scb.pi_debug[35:34] <= 2'b00;
end end
if (reset) begin if (reset) begin
@ -368,9 +380,9 @@ module n64_pi (
if (write_op) begin if (write_op) begin
if (write_fifo_full) begin if (write_fifo_full) begin
write_fifo_wait <= 1'b1; write_fifo_wait <= 1'b1;
n64_scb.pi_debug[2] <= 1'b1; n64_scb.pi_debug[34] <= 1'b1;
if (write_fifo_wait) begin if (write_fifo_wait) begin
n64_scb.pi_debug[3] <= 1'b1; n64_scb.pi_debug[35] <= 1'b1;
end end
end else begin end else begin
write_fifo_write <= 1'b1; write_fifo_write <= 1'b1;

2
fw/rtl/n64/n64_scb.sv
View File

@ -53,7 +53,7 @@ interface n64_scb ();
logic pi_sdram_active; logic pi_sdram_active;
logic pi_flash_active; logic pi_flash_active;
logic [3:0] pi_debug; logic [35:0] pi_debug;
modport controller ( modport controller (
input n64_reset, input n64_reset,

3
sw/controller/src/cfg.c
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@ -569,7 +569,8 @@ void cfg_process (void) {
break; break;
case '?': case '?':
args[0] = fpga_reg_get(REG_DEBUG); args[0] = fpga_reg_get(REG_DEBUG_0);
args[1] = fpga_reg_get(REG_DEBUG_1);
break; break;
default: default:

3
sw/controller/src/fpga.h
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@ -52,7 +52,8 @@ typedef enum {
REG_DD_DRIVE_ID, REG_DD_DRIVE_ID,
REG_VENDOR_SCR, REG_VENDOR_SCR,
REG_VENDOR_DATA, REG_VENDOR_DATA,
REG_DEBUG REG_DEBUG_0,
REG_DEBUG_1,
} fpga_reg_t; } fpga_reg_t;

5
sw/controller/src/usb.c
View File

@ -288,8 +288,9 @@ static void usb_rx_process (void) {
case '?': case '?':
p.rx_state = RX_STATE_IDLE; p.rx_state = RX_STATE_IDLE;
p.response_pending = true; p.response_pending = true;
p.response_info.data_length = 4; p.response_info.data_length = 8;
p.response_info.data[0] = fpga_reg_get(REG_DEBUG); p.response_info.data[0] = fpga_reg_get(REG_DEBUG_0);
p.response_info.data[1] = fpga_reg_get(REG_DEBUG_1);
break; break;
default: default: