Commit Graph

5 Commits

Author SHA1 Message Date
Polprzewodnikowy
2121b00e3d rtc 2 bit clock stop support 2022-10-12 01:15:19 +02:00
Polprzewodnikowy
0b18c55d1c changed mem addressing 2022-07-30 19:39:49 +02:00
Polprzewodnikowy
470b61aad9 pre DMA rewrite, created dedicated buffer memory space, simplified code 2022-07-18 21:15:19 +02:00
Polprzewodnikowy
ab9bd74e91 backup 2022-05-15 15:47:12 +02:00
Mateusz Faderewski
45fbd53001
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5) 2021-09-25 20:00:36 +02:00