mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-12-12 14:44:17 +01:00
287 lines
5.5 KiB
Systemverilog
287 lines
5.5 KiB
Systemverilog
module top (
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input inclk,
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input n64_reset,
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input n64_nmi,
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output n64_irq,
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input n64_pi_alel,
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input n64_pi_aleh,
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input n64_pi_read,
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input n64_pi_write,
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inout [15:0] n64_pi_ad,
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input n64_si_clk,
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inout n64_si_dq,
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input n64_cic_clk,
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inout n64_cic_dq,
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input usb_pwrsav,
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output usb_clk,
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output usb_cs,
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input usb_miso,
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inout [7:0] usb_miosi,
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input sd_det,
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output sd_clk,
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inout sd_cmd,
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inout [3:0] sd_dat,
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output sdram_clk,
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output sdram_cs,
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output sdram_ras,
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output sdram_cas,
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output sdram_we,
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output [1:0] sdram_ba,
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output [12:0] sdram_a,
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output [1:0] sdram_dqm,
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inout [15:0] sdram_dq,
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output flash_clk,
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output flash_cs,
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inout [3:0] flash_dq,
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input button,
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output mcu_int,
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input mcu_clk,
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input mcu_cs,
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input mcu_mosi,
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output mcu_miso,
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// Unused I/O
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output n64_video_sync,
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output [2:0] test_point
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);
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logic clk;
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logic reset;
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n64_scb n64_scb ();
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dd_scb dd_scb ();
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usb_scb usb_scb ();
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dma_scb usb_dma_scb ();
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sd_scb sd_scb ();
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dma_scb sd_dma_scb ();
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flash_scb flash_scb ();
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vendor_scb vendor_scb ();
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fifo_bus usb_cfg_fifo_bus ();
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fifo_bus usb_dma_fifo_bus ();
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fifo_bus usb_fifo_bus ();
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fifo_bus sd_fifo_bus ();
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mem_bus n64_mem_bus ();
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mem_bus cfg_mem_bus ();
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mem_bus usb_dma_mem_bus ();
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mem_bus sd_dma_mem_bus ();
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mem_bus sdram_mem_bus ();
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mem_bus flash_mem_bus ();
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mem_bus bram_mem_bus ();
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pll pll_inst (
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.inclk(inclk),
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.clk(clk),
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.sdram_clk(sdram_clk),
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.reset(reset)
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);
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// MCU controller
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mcu_top mcu_top_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb),
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.dd_scb(dd_scb),
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.usb_scb(usb_scb),
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.usb_dma_scb(usb_dma_scb),
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.sd_scb(sd_scb),
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.sd_dma_scb(sd_dma_scb),
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.flash_scb(flash_scb),
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.vendor_scb(vendor_scb),
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.fifo_bus(usb_cfg_fifo_bus),
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.mem_bus(cfg_mem_bus),
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.sd_det(sd_det),
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.button(button),
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.mcu_int(mcu_int),
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.mcu_clk(mcu_clk),
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.mcu_cs(mcu_cs),
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.mcu_mosi(mcu_mosi),
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.mcu_miso(mcu_miso)
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);
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// N64 controller
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n64_top n64_top_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb),
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.dd_scb(dd_scb),
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.mem_bus(n64_mem_bus),
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.n64_reset(n64_reset),
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.n64_nmi(n64_nmi),
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.n64_irq(n64_irq),
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.n64_pi_alel(n64_pi_alel),
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.n64_pi_aleh(n64_pi_aleh),
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.n64_pi_read(n64_pi_read),
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.n64_pi_write(n64_pi_write),
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.n64_pi_ad(n64_pi_ad),
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.n64_si_clk(n64_si_clk),
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.n64_si_dq(n64_si_dq),
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.n64_cic_clk(n64_cic_clk),
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.n64_cic_dq(n64_cic_dq)
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);
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// USB
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usb_ft1248 usb_ft1248_inst (
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.clk(clk),
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.reset(reset),
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.usb_scb(usb_scb),
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.fifo_bus(usb_fifo_bus),
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.usb_pwrsav(usb_pwrsav),
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.usb_clk(usb_clk),
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.usb_cs(usb_cs),
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.usb_miso(usb_miso),
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.usb_miosi(usb_miosi)
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);
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memory_dma memory_usb_dma_inst (
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.clk(clk),
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.reset(reset),
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.dma_scb(usb_dma_scb),
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.fifo_bus(usb_dma_fifo_bus),
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.mem_bus(usb_dma_mem_bus)
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);
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fifo_junction usb_fifo_junction_inst (
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.cfg_bus(usb_cfg_fifo_bus),
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.dma_bus(usb_dma_fifo_bus),
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.dev_bus(usb_fifo_bus)
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);
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// SD card
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sd_top sd_top_inst (
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.clk(clk),
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.reset(reset),
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.sd_scb(sd_scb),
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.fifo_bus(sd_fifo_bus),
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.sd_clk(sd_clk),
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.sd_cmd(sd_cmd),
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.sd_dat(sd_dat)
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);
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memory_dma memory_sd_dma_inst (
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.clk(clk),
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.reset(reset),
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.dma_scb(sd_dma_scb),
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.fifo_bus(sd_fifo_bus),
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.mem_bus(sd_dma_mem_bus)
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);
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// Memory bus arbiter
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memory_arbiter memory_arbiter_inst (
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.clk(clk),
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.reset(reset),
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.n64_scb(n64_scb),
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.n64_bus(n64_mem_bus),
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.cfg_bus(cfg_mem_bus),
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.usb_dma_bus(usb_dma_mem_bus),
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.sd_dma_bus(sd_dma_mem_bus),
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.sdram_mem_bus(sdram_mem_bus),
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.flash_mem_bus(flash_mem_bus),
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.bram_mem_bus(bram_mem_bus)
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);
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// Memory controllers
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memory_sdram memory_sdram_inst (
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.clk(clk),
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.reset(reset),
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.mem_bus(sdram_mem_bus),
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.sdram_cs(sdram_cs),
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.sdram_ras(sdram_ras),
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.sdram_cas(sdram_cas),
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.sdram_we(sdram_we),
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.sdram_ba(sdram_ba),
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.sdram_a(sdram_a),
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.sdram_dqm(sdram_dqm),
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.sdram_dq(sdram_dq)
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);
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memory_flash memory_flash_inst (
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.clk(clk),
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.reset(reset),
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.flash_scb(flash_scb),
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.mem_bus(flash_mem_bus),
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.flash_clk(flash_clk),
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.flash_cs(flash_cs),
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.flash_dq(flash_dq)
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);
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memory_bram memory_bram_inst (
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.clk(clk),
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.n64_scb(n64_scb),
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.mem_bus(bram_mem_bus)
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);
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// Vendor specific control
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vendor vendor_inst (
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.clk(clk),
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.reset(reset),
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.vendor_scb(vendor_scb)
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);
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// Unused I/O
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assign n64_video_sync = 1'bZ;
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assign test_point = 3'b000;
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endmodule
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