Mateusz Faderewski 2a33bffd72 register PI reg bus

2024-06-12 02:21:13 +02:00

..

n64_cfg.sv

fw irq improvements (force high state for one clock when de-asserting irq)

2024-05-22 00:10:33 +02:00

n64_cic.sv

[SC64][FW] CIC: use output enable register in PIO

2024-05-03 17:51:20 +02:00

n64_dd.sv

[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)

2022-11-10 11:46:54 +01:00

n64_flashram.sv

[SC64][FW][SW] Controller rewrite to remove task subsystem + minor bug fixes (#64)

2024-01-29 14:23:18 +01:00

n64_pi_fifo.sv

[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)

2022-11-10 11:46:54 +01:00

n64_pi.sv

register PI reg bus

2024-06-12 02:21:13 +02:00

n64_reg_bus.sv

[SC64][FW][HW][SW] New version based on LCMXO2 FPGA (#19)

2022-11-10 11:46:54 +01:00

n64_save_counter.sv

[SC64][FW] Added save write count register for SD save writeback

2022-11-24 22:55:05 +01:00

n64_scb.sv

[SC64][FW][SW] Added option to set and read century when updating RTC datetime

2024-06-06 23:00:38 +02:00

n64_si.sv

[SC64][FW][SW] Added option to set and read century when updating RTC datetime

2024-06-06 23:00:38 +02:00

n64_top.sv

fw irq improvements (force high state for one clock when de-asserting irq)

2024-05-22 00:10:33 +02:00