Mateusz Faderewski 598a4205bb more IRQ sources + AUX data channel		2024-08-05 22:16:46 +02:00
..
fifo	[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)	2024-07-21 11:15:08 +02:00
mcu	more IRQ sources + AUX data channel	2024-08-05 22:16:46 +02:00
memory	[SC64][FW][SW] Slightly speed up DMA write transfer speed + USB speed test fixes	2024-07-21 22:15:06 +02:00
n64	more IRQ sources + AUX data channel	2024-08-05 22:16:46 +02:00
sd	[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)	2024-07-21 11:15:08 +02:00
serv	[SC64][FW][SW] Moved CIC emulation from MCU to FPGA (#56)	2023-12-14 19:26:54 +01:00
usb	[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)	2024-07-21 11:15:08 +02:00
vendor	[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)	2024-07-21 11:15:08 +02:00
top.sv	[SC64][FW] Added placeholder test point outputs in the FPGA project	2024-05-03 17:55:40 +02:00