Polprzewodnikowy 7f9989cab6 fsd write, rtc, isv and reset fixes

2022-01-23 19:56:28 +01:00

..

cfg.c

fsd write, rtc, isv and reset fixes

2022-01-23 19:56:28 +01:00

cfg.h

fsd write, rtc, isv and reset fixes

2022-01-23 19:56:28 +01:00

dd.c

little cleanup

2022-01-22 01:25:48 +01:00

dd.h

super slow usb storage reading implemented

2022-01-21 21:29:41 +01:00

dma.c

[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)

2021-11-16 22:37:48 +01:00

dma.h

[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)

2021-11-16 22:37:48 +01:00

flash.c

[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)

2021-12-10 17:36:30 +01:00

flash.h

[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)

2021-12-10 17:36:30 +01:00

flashram.c

[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)

2021-11-16 22:37:48 +01:00

flashram.h

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

i2c.c

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

i2c.h

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

isv.c

fsd write, rtc, isv and reset fixes

2022-01-23 19:56:28 +01:00

isv.h

isv support + usb/dd improvements

2021-12-27 00:01:07 +01:00

joybus.c

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

joybus.h

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

process.c

isv support + usb/dd improvements

2021-12-27 00:01:07 +01:00

process.h

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

rtc.c

[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)

2021-11-16 22:37:48 +01:00

rtc.h

[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)

2021-09-25 20:00:36 +02:00

startup.S

[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)

2021-12-10 17:36:30 +01:00

sys.h

ISV in hardware finally

2022-01-22 23:19:07 +01:00

uart.c

mooore cleanup

2022-01-15 01:21:33 +01:00

uart.h

mooore cleanup

2022-01-15 01:21:33 +01:00

usb.c

fsd write, rtc, isv and reset fixes

2022-01-23 19:56:28 +01:00

usb.h

removed separate event id

2022-01-22 15:56:20 +01:00