The-Homebrew-Cloud/SummerCart64
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SummerCart64/sw/riscv/src
History
Polprzewodnikowy c2ae1e2587 removed separate event id
2022-01-22 15:56:20 +01:00
..
cfg.c
double buffered reads
2022-01-22 13:03:05 +01:00
cfg.h
[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
2021-12-10 17:36:30 +01:00
dd.c
little cleanup
2022-01-22 01:25:48 +01:00
dd.h
super slow usb storage reading implemented
2022-01-21 21:29:41 +01:00
dma.c
[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
2021-11-16 22:37:48 +01:00
dma.h
[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
2021-11-16 22:37:48 +01:00
flash.c
[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
2021-12-10 17:36:30 +01:00
flash.h
[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
2021-12-10 17:36:30 +01:00
flashram.c
[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
2021-11-16 22:37:48 +01:00
flashram.h
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
i2c.c
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
i2c.h
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
isv.c
super slow usb storage reading implemented
2022-01-21 21:29:41 +01:00
isv.h
isv support + usb/dd improvements
2021-12-27 00:01:07 +01:00
joybus.c
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
joybus.h
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
process.c
isv support + usb/dd improvements
2021-12-27 00:01:07 +01:00
process.h
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
rtc.c
[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
2021-11-16 22:37:48 +01:00
rtc.h
[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
2021-09-25 20:00:36 +02:00
startup.S
[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
2021-12-10 17:36:30 +01:00
sys.h
double buffered reads
2022-01-22 13:03:05 +01:00
uart.c
mooore cleanup
2022-01-15 01:21:33 +01:00
uart.h
mooore cleanup
2022-01-15 01:21:33 +01:00
usb.c
removed separate event id
2022-01-22 15:56:20 +01:00
usb.h
removed separate event id
2022-01-22 15:56:20 +01:00