mirror of
https://github.com/Polprzewodnikowy/SummerCart64.git
synced 2024-11-26 07:34:15 +01:00
87 lines
2.3 KiB
Verilog
87 lines
2.3 KiB
Verilog
// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (100) @(posedge clk);
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resetn <= 1;
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repeat (1000) @(posedge clk);
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$finish;
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end
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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always @(posedge clk) begin
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if (mem_valid && mem_ready) begin
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if (mem_instr)
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$display("ifetch 0x%08x: 0x%08x", mem_addr, mem_rdata);
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else if (mem_wstrb)
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$display("write 0x%08x: 0x%08x (wstrb=%b)", mem_addr, mem_wdata, mem_wstrb);
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else
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$display("read 0x%08x: 0x%08x", mem_addr, mem_rdata);
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end
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end
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picorv32 #(
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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reg [31:0] memory [0:255];
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initial begin
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memory[0] = 32'h 3fc00093; // li x1,1020
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memory[1] = 32'h 0000a023; // sw x0,0(x1)
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memory[2] = 32'h 0000a103; // loop: lw x2,0(x1)
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memory[3] = 32'h 00110113; // addi x2,x2,1
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memory[4] = 32'h 0020a023; // sw x2,0(x1)
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memory[5] = 32'h ff5ff06f; // j <loop>
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end
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always @(posedge clk) begin
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mem_ready <= 0;
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if (mem_valid && !mem_ready) begin
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if (mem_addr < 1024) begin
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mem_ready <= 1;
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mem_rdata <= memory[mem_addr >> 2];
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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/* add memory-mapped IO here */
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end
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end
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endmodule
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