| .. |
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cfg.c
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super slow usb storage reading implemented
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2022-01-21 21:29:41 +01:00 |
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cfg.h
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[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
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2021-12-10 17:36:30 +01:00 |
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dd.c
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little cleanup
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2022-01-22 01:25:48 +01:00 |
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dd.h
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super slow usb storage reading implemented
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2022-01-21 21:29:41 +01:00 |
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dma.c
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[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
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2021-11-16 22:37:48 +01:00 |
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dma.h
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[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
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2021-11-16 22:37:48 +01:00 |
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flash.c
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[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
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2021-12-10 17:36:30 +01:00 |
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flash.h
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[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
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2021-12-10 17:36:30 +01:00 |
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flashram.c
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[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
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2021-11-16 22:37:48 +01:00 |
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flashram.h
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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i2c.c
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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i2c.h
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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isv.c
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super slow usb storage reading implemented
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2022-01-21 21:29:41 +01:00 |
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isv.h
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isv support + usb/dd improvements
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2021-12-27 00:01:07 +01:00 |
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joybus.c
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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joybus.h
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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process.c
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isv support + usb/dd improvements
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2021-12-27 00:01:07 +01:00 |
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process.h
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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rtc.c
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[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional module (#12)
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2021-11-16 22:37:48 +01:00 |
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rtc.h
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[SC64][FW][SW] Complete fw/sw rewrite with RISC-V softcore CPU as flashcart controller (#5)
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2021-09-25 20:00:36 +02:00 |
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startup.S
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[SC64][FW][SW] Added escape mechanism in USB, changed N64 boot procedure, added "fake SD card through USB" feature, rewritten PC communication software (#13)
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2021-12-10 17:36:30 +01:00 |
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sys.h
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usb gets fast
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2022-01-22 00:10:47 +01:00 |
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uart.c
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mooore cleanup
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2022-01-15 01:21:33 +01:00 |
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uart.h
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mooore cleanup
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2022-01-15 01:21:33 +01:00 |
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usb.c
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little cleanup
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2022-01-22 01:25:48 +01:00 |
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usb.h
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super slow usb storage reading implemented
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2022-01-21 21:29:41 +01:00 |
