mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-01-24 06:51:17 +01:00
More 32-bit speed
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@164 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
parent
12b37ba323
commit
c305371725
@ -669,6 +669,10 @@ namespace Gen
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void MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
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{
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "MOVSX - Imm argument");
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if (dbits == sbits) {
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MOV(dbits, R(dest), src);
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return;
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}
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src.operandReg = (u8)dest;
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if (dbits == 16) Write8(0x66);
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src.WriteRex(dbits == 64);
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@ -696,6 +700,10 @@ namespace Gen
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void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
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{
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "MOVZX - Imm argument");
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if (dbits == sbits) {
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MOV(dbits, R(dest), src);
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return;
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}
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src.operandReg = (u8)dest;
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if (dbits == 16) Write8(0x66);
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src.WriteRex(dbits == 64);
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@ -346,7 +346,7 @@ void CInterpreter::srawx(UGeckoInstruction _inst)
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}
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else
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{
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int amount = rb&0x1f;
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int amount = rb & 0x1f;
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if (amount == 0)
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{
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m_GPR[_inst.RA] = m_GPR[_inst.RS];
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@ -115,13 +115,13 @@ void CInterpreter::lfsx(UGeckoInstruction _inst)
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void CInterpreter::lha(UGeckoInstruction _inst)
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{
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m_GPR[_inst.RD] = (u32)(s16)Memory::Read_U16(Helper_Get_EA(_inst));
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m_GPR[_inst.RD] = (u32)(s32)(s16)Memory::Read_U16(Helper_Get_EA(_inst));
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}
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void CInterpreter::lhau(UGeckoInstruction _inst)
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{
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u32 uAddress = Helper_Get_EA_U(_inst);
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m_GPR[_inst.RD] = (u32)(s16)Memory::Read_U16(uAddress);
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m_GPR[_inst.RD] = (u32)(s32)(s16)Memory::Read_U16(uAddress);
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m_GPR[_inst.RA] = uAddress;
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}
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@ -188,6 +188,7 @@ detect immediates in stb stw sth
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TODO
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lha
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srawx
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addic_rc
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addex
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subfcx
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@ -86,7 +86,10 @@ namespace Jit64
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void FlushRegCaches();
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void SafeLoadRegToEAX(Gen::X64Reg reg, int accessSize, s32 offset);
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void UnsafeLoadRegToReg(Gen::X64Reg reg_addr, Gen::X64Reg reg_value, int accessSize, s32 offset = 0, bool signExtend = false);
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void UnsafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset = 0);
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void SafeLoadRegToEAX(Gen::X64Reg reg, int accessSize, s32 offset, bool signExtend = false);
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void SafeWriteRegToReg(Gen::X64Reg reg_value, Gen::X64Reg reg_addr, int accessSize, s32 offset);
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void addx(UGeckoInstruction inst);
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void orx(UGeckoInstruction inst);
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@ -144,6 +147,7 @@ namespace Jit64
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void fmaddXX(UGeckoInstruction inst);
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void stX(UGeckoInstruction inst); //stw sth stb
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void lXz(UGeckoInstruction inst);
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void lha(UGeckoInstruction inst);
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void rlwinmx(UGeckoInstruction inst);
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void rlwimix(UGeckoInstruction inst);
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void rlwnmx(UGeckoInstruction inst);
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@ -153,6 +157,7 @@ namespace Jit64
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void dcbz(UGeckoInstruction inst);
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void lfsx(UGeckoInstruction inst);
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void subfic(UGeckoInstruction inst);
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void subfcx(UGeckoInstruction inst);
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void subfx(UGeckoInstruction inst);
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void lbzx(UGeckoInstruction inst);
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@ -29,45 +29,56 @@
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namespace Jit64
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{
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// Assumes that the flags were just set through an addition.
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void GenerateCarry(X64Reg temp_reg) {
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SETcc(CC_C, R(temp_reg));
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AND(32, M(&XER), Imm32(~(1 << 29)));
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SHL(32, R(temp_reg), Imm8(29));
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OR(32, M(&XER), R(temp_reg));
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}
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typedef u32 (*Operation)(u32 a, u32 b);
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u32 Add(u32 a, u32 b) {return a + b;}
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u32 Or (u32 a, u32 b) {return a | b;}
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u32 And(u32 a, u32 b) {return a & b;}
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u32 Xor(u32 a, u32 b) {return a ^ b;}
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void regimmop(int d, int a, bool binary, u32 value, Operation doop, void(*op)(int, const OpArg&, const OpArg&), bool Rc = false)
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void regimmop(int d, int a, bool binary, u32 value, Operation doop, void(*op)(int, const OpArg&, const OpArg&), bool Rc = false, bool carry = false)
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{
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gpr.Lock(d,a);
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if (a || binary)
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if (a || binary || carry) // yeh nasty special case addic
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{
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if (a == d)
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{
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if (gpr.R(d).IsImm())
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if (gpr.R(d).IsImm() && !carry)
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{
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gpr.SetImmediate32(d, doop((u32)gpr.R(d).offset, value));
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}
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else
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{
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if (gpr.R(d).IsImm())
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gpr.LoadToX64(d,false);
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gpr.LoadToX64(d, false);
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op(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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if (carry)
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GenerateCarry(EAX);
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}
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}
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else
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{
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gpr.LoadToX64(d,false);
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gpr.LoadToX64(d, false);
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MOV(32, gpr.R(d), gpr.R(a));
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op(32, gpr.R(d), Imm32(value)); //m_GPR[d] = m_GPR[_inst.RA] + _inst.SIMM_16;
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if (carry)
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GenerateCarry(EAX);
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}
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}
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else if (doop == Add)
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else if (doop == Add && !carry)
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{
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gpr.SetImmediate32(d, value);
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}
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else
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{
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_assert_msg_(DYNA_REC, 0, "WTF");
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_assert_msg_(DYNA_REC, 0, "WTF regimmop");
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}
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if (Rc)
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{
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@ -95,8 +106,8 @@ namespace Jit64
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case 29: regimmop(a, s, true, inst.UIMM << 16, And, AND, true); break;
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case 26: regimmop(a, s, true, inst.UIMM, Xor, XOR, false); break; //xori
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case 27: regimmop(a, s, true, inst.UIMM << 16, Xor, XOR, false); break; //xoris
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case 12: //addic
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case 13: //addic_rc
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case 12: //regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, ADD, false, true); //addic
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case 13: //regimmop(d, a, true, (u32)(s32)inst.SIMM_16, Add, ADD, true, true); //addic_rc
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default:
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Default(inst);
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break;
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@ -314,20 +325,32 @@ namespace Jit64
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else
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gpr.LoadToX64(a, true, true);
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int imm = inst.SIMM_16;
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// XOR(32, R(ECX), R(ECX));
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MOV(32, R(EAX), gpr.R(a));
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NOT(32, R(EAX));
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ADD(32, R(EAX), Imm32(imm+1));
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MOV(32, gpr.R(d), R(EAX));
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SETcc(CC_C, R(ECX));
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AND(32, M(&XER), Imm32(~(1 << 29)));
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SHL(32, R(ECX), Imm8(29));
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OR(32, M(&XER), R(ECX));
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GenerateCarry(ECX);
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gpr.UnlockAll();
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gpr.UnlockAllX();
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// This instruction has no RC flag
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}
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void subfcx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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Default(inst);
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return;
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/*
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u32 a = m_GPR[_inst.RA];
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u32 b = m_GPR[_inst.RB];
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m_GPR[_inst.RD] = b - a;
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SetCarry(a == 0 || Helper_Carry(b, 0-a));
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if (_inst.OE) PanicAlert("OE: subfcx");
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if (_inst.Rc) Helper_UpdateCR0(m_GPR[_inst.RD]);
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*/
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}
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void subfx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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@ -447,9 +470,6 @@ namespace Jit64
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}
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}
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// __________________________________________________________________________________________________
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// Helper_Mask
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//
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u32 Helper_Mask(u8 mb, u8 me)
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{
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return (((mb > me) ?
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@ -459,7 +479,6 @@ namespace Jit64
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);
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}
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void addx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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@ -527,10 +546,7 @@ namespace Jit64
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MOV(32, R(EAX), gpr.R(a));
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ADC(32, R(EAX), gpr.R(b));
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MOV(32, gpr.R(d), R(EAX));
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SETcc(CC_C, R(ECX)); // store away the resulting carry flag
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AND(32, M(&XER), Imm32(~(1 << 29)));
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SHL(32, R(ECX), Imm8(29));
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OR(32, M(&XER), R(ECX));
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GenerateCarry(ECX);
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gpr.UnlockAll();
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gpr.UnlockAllX();
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if (inst.Rc)
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@ -49,27 +49,35 @@ namespace Jit64
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static u64 GC_ALIGNED16(temp64);
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static u32 GC_ALIGNED16(temp32);
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void SafeLoadRegToEAX(X64Reg reg, int accessSize, s32 offset)
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void UnsafeLoadRegToReg(X64Reg reg_addr, X64Reg reg_value, int accessSize, s32 offset, bool signExtend)
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{
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if (offset)
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ADD(32, R(reg), Imm32((u32)offset));
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TEST(32, R(reg), Imm32(0x0C000000));
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FixupBranch argh = J_CC(CC_NZ);
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if (accessSize != 32)
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XOR(32, R(EAX), R(EAX));
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#ifdef _M_IX86
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AND(32, R(reg), Imm32(Memory::MEMVIEW32_MASK));
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MOV(accessSize, R(EAX), MDisp(reg, (u32)Memory::base));
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AND(32, R(reg_addr), Imm32(Memory::MEMVIEW32_MASK));
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MOVZX(32, accessSize, reg_value, MDisp(reg_addr, (u32)Memory::base + offset));
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#else
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MOV(accessSize, R(EAX), MComplex(RBX, reg, SCALE_1, 0));
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MOVZX(32, accessSize, reg_value, MComplex(RBX, reg_addr, SCALE_1, offset));
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#endif
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if (accessSize == 32)
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{
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BSWAP(32, EAX);
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}
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else if (accessSize == 16)
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{
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BSWAP(32, EAX);
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SHR(32, R(EAX), Imm8(16));
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}
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if (signExtend && accessSize < 32) {
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MOVSX(32, accessSize, EAX, R(EAX));
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}
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}
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void SafeLoadRegToEAX(X64Reg reg, int accessSize, s32 offset, bool signExtend)
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{
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if (offset)
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ADD(32, R(reg), Imm32((u32)offset));
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TEST(32, R(reg), Imm32(0x0C000000));
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FixupBranch argh = J_CC(CC_NZ);
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UnsafeLoadRegToReg(reg, EAX, accessSize, 0, signExtend);
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FixupBranch arg2 = J();
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SetJumpTarget(argh);
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switch (accessSize)
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@ -81,6 +89,34 @@ namespace Jit64
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SetJumpTarget(arg2);
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}
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void UnsafeWriteRegToReg(X64Reg reg_value, X64Reg reg_addr, int accessSize, s32 offset)
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{
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if (accessSize != 32) {
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PanicAlert("UnsafeWriteRegToReg can't handle %i byte accesses", accessSize);
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}
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BSWAP(32, reg_value);
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#ifdef _M_IX86
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AND(32, R(reg_addr), Imm32(Memory::MEMVIEW32_MASK));
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MOV(accessSize, MDisp(reg_addr, (u32)Memory::base), R(reg_value));
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#else
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MOV(accessSize, MComplex(RBX, reg_addr, SCALE_1, 0), R(reg_value));
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#endif
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}
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// Destroys both arg registers
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void SafeWriteRegToReg(X64Reg reg_value, X64Reg reg_addr, int accessSize, s32 offset)
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{
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if (offset)
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ADD(32, R(reg_addr), Imm32(offset));
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TEST(32, R(reg_addr), Imm32(0x0C000000));
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FixupBranch argh = J_CC(CC_NZ);
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UnsafeWriteRegToReg(reg_value, reg_addr, accessSize, 0);
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FixupBranch arg2 = J();
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SetJumpTarget(argh);
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ABI_CallFunctionRR((void *)&Memory::Write_U32, ABI_PARAM1, ABI_PARAM2);
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SetJumpTarget(arg2);
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}
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void lbzx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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@ -146,6 +182,7 @@ namespace Jit64
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#endif
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// Safe and boring
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gpr.Flush(FLUSH_VOLATILE);
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fpr.Flush(FLUSH_VOLATILE);
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gpr.Lock(d, a);
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MOV(32, R(ABI_PARAM1), gpr.R(a));
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SafeLoadRegToEAX(ABI_PARAM1, accessSize, offset);
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@ -173,6 +210,24 @@ namespace Jit64
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gpr.UnlockAll();
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}
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void lha(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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int d = inst.RD;
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int a = inst.RA;
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s32 offset = (s32)(s16)inst.SIMM_16;
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// Safe and boring
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gpr.Flush(FLUSH_VOLATILE);
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fpr.Flush(FLUSH_VOLATILE);
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gpr.Lock(d, a);
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MOV(32, R(ABI_PARAM1), gpr.R(a));
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SafeLoadRegToEAX(ABI_PARAM1, 16, offset, true);
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gpr.LoadToX64(d, false, true);
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MOV(32, gpr.R(d), R(EAX));
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gpr.UnlockAll();
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return;
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}
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// Zero cache line.
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void dcbz(UGeckoInstruction inst)
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{
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@ -70,17 +70,11 @@ void lfs(UGeckoInstruction inst)
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gpr.Lock(d, a);
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MOV(32, R(ABI_PARAM1), gpr.R(a));
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#ifdef _M_X64
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if (!jo.noAssumeFPLoadFromMem)
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{
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MOV(32, R(EAX), MComplex(RBX, ABI_PARAM1, SCALE_1, offset));
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//#else
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// MOV(32, R(EAX), MDisp(ABI_PARAM1, (u32)Memory::GetMainRAMPtr() + (u32)offset));
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//#endif
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BSWAP(32, EAX);
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UnsafeLoadRegToReg(ABI_PARAM1, EAX, 32, offset, false);
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}
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else
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#endif
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{
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SafeLoadRegToEAX(ABI_PARAM1, 32, offset);
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}
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@ -145,7 +139,6 @@ void stfd(UGeckoInstruction inst)
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void stfs(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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DISABLE_32BIT;
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bool update = inst.OPCD & 1;
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int s = inst.RS;
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int a = inst.RA;
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@ -156,9 +149,8 @@ void stfs(UGeckoInstruction inst)
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gpr.Flush(FLUSH_VOLATILE);
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gpr.Lock(a);
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fpr.Lock(s);
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gpr.LockX(ABI_PARAM1, ABI_PARAM2);
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MOV(32, R(ABI_PARAM2), gpr.R(a));
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if (offset)
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ADD(32, R(ABI_PARAM2), Imm32((u32)offset));
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if (update && offset)
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{
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MOV(32, gpr.R(a), R(ABI_PARAM2));
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@ -167,15 +159,9 @@ void stfs(UGeckoInstruction inst)
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MOVSS(M(&temp32), XMM0);
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MOV(32, R(ABI_PARAM1), M(&temp32));
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TEST(32, R(ABI_PARAM2), Imm32(0x0C000000));
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FixupBranch argh = J_CC(CC_NZ);
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BSWAP(32, ABI_PARAM1);
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MOV(32, MComplex(RBX, ABI_PARAM2, SCALE_1, 0), R(ABI_PARAM1));
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FixupBranch arg2 = J();
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SetJumpTarget(argh);
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CALL((void *)&Memory::Write_U32);
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SetJumpTarget(arg2);
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SafeWriteRegToReg(ABI_PARAM1, ABI_PARAM2, 32, offset);
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gpr.UnlockAll();
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gpr.UnlockAllX();
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fpr.UnlockAll();
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}
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else
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@ -187,14 +173,12 @@ void stfs(UGeckoInstruction inst)
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void lfsx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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DISABLE_32BIT;
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fpr.Lock(inst.RS);
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fpr.LoadToX64(inst.RS, false, true);
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MOV(32, R(EAX), gpr.R(inst.RB));
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if (inst.RA)
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ADD(32, R(EAX), gpr.R(inst.RA));
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MOV(32, R(EAX), MComplex(RBX, EAX, SCALE_1, 0));
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BSWAP(32, EAX);
|
||||
UnsafeLoadRegToReg(EAX, EAX, 32, false);
|
||||
MOV(32, M(&temp32), R(EAX));
|
||||
CVTSS2SD(XMM0, M(&temp32));
|
||||
MOVDDUP(fpr.R(inst.RS).GetSimpleReg(), R(XMM0));
|
||||
|
||||
@ -144,8 +144,8 @@ GekkoOPTemplate primarytable[] =
|
||||
{8, CInterpreter::subfic, Jit64::subfic, {"subfic", OPTYPE_INTEGER, FL_SET_CA}},
|
||||
{10, CInterpreter::cmpli, Jit64::cmpli, {"cmpli", OPTYPE_INTEGER, FL_SET_CRn}},
|
||||
{11, CInterpreter::cmpi, Jit64::cmpi, {"cmpi", OPTYPE_INTEGER, FL_SET_CRn}},
|
||||
{12, CInterpreter::addic, Jit64::Default, {"addic", OPTYPE_INTEGER, FL_SET_CA}},
|
||||
{13, CInterpreter::addic_rc, Jit64::Default, {"addic_rc", OPTYPE_INTEGER, FL_SET_CR0}},
|
||||
{12, CInterpreter::addic, Jit64::reg_imm, {"addic", OPTYPE_INTEGER, FL_SET_CA}},
|
||||
{13, CInterpreter::addic_rc, Jit64::reg_imm, {"addic_rc", OPTYPE_INTEGER, FL_SET_CR0}},
|
||||
{14, CInterpreter::addi, Jit64::reg_imm, {"addi", OPTYPE_INTEGER, 0}},
|
||||
{15, CInterpreter::addis, Jit64::reg_imm, {"addis", OPTYPE_INTEGER, 0}},
|
||||
|
||||
@ -166,7 +166,7 @@ GekkoOPTemplate primarytable[] =
|
||||
{35, CInterpreter::lbzu, Jit64::Default, {"lbzu", OPTYPE_LOAD, 0}},
|
||||
{40, CInterpreter::lhz, Jit64::lXz, {"lhz", OPTYPE_LOAD, 0}},
|
||||
{41, CInterpreter::lhzu, Jit64::Default, {"lhzu", OPTYPE_LOAD, 0}},
|
||||
{42, CInterpreter::lha, Jit64::Default, {"lha", OPTYPE_LOAD, 0}},
|
||||
{42, CInterpreter::lha, Jit64::lha, {"lha", OPTYPE_LOAD, 0}},
|
||||
{43, CInterpreter::lhau, Jit64::Default, {"lhau", OPTYPE_LOAD, 0}},
|
||||
|
||||
{48, CInterpreter::lfs, Jit64::lfs, {"lfs", OPTYPE_LOADFP, 0}},
|
||||
@ -398,7 +398,7 @@ GekkoOPTemplate table31_2[] =
|
||||
{235, CInterpreter::mullwx, Jit64::mullwx, {"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT, 4}},
|
||||
{104, CInterpreter::negx, Jit64::negx, {"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}},
|
||||
{40, CInterpreter::subfx, Jit64::subfx, {"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_RC_BIT}},
|
||||
{8, CInterpreter::subfcx, Jit64::Default, {"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_SET_CA | FL_RC_BIT}},
|
||||
{8, CInterpreter::subfcx, Jit64::subfcx, {"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_SET_CA | FL_RC_BIT}},
|
||||
{136, CInterpreter::subfex, Jit64::Default, {"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
|
||||
{232, CInterpreter::subfmex, Jit64::Default, {"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
|
||||
{200, CInterpreter::subfzex, Jit64::Default, {"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_IN_B | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user