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JitArm64: Cram two constants into one register

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This commit is contained in:
JosJuice 2022-10-18 22:18:53 +02:00
parent 79f856a8d1
commit cd027f4091
5 changed files with 8 additions and 9 deletions
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4
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -575,8 +575,8 @@ void JitArm64::fctiwx(UGeckoInstruction inst)
m_float_emit.FCVTS(EncodeRegToSingle(VD), EncodeRegToSingle(VD), RoundingMode::Z); m_float_emit.FCVTS(EncodeRegToSingle(VD), EncodeRegToSingle(VD), RoundingMode::Z);
} }
m_float_emit.ORR(EncodeRegToDouble(VD), EncodeRegToDouble(VD), m_float_emit.INS(32, EncodeRegToDouble(VD), 1,
EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_0000_0000)); EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_3F80_0000), 1);
} }
else else
{ {

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
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@ -121,7 +121,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
if (w) if (w)
{ {
// Set ps1 to 1.0 // Set ps1 to 1.0
m_float_emit.INS(32, VS, 1, FPR_CONSTANT_0000_0000_3F80_0000, 0); m_float_emit.INS(32, VS, 1, FPR_CONSTANT_FFF8_0000_3F80_0000, 0);
} }
const ARM64Reg VS_again = fpr.RW(inst.RS, RegType::Single, true); const ARM64Reg VS_again = fpr.RW(inst.RS, RegType::Single, true);

1
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
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@ -726,6 +726,7 @@ void Arm64FPRCache::GetAllocationOrder()
ARM64Reg::Q10, ARM64Reg::Q10,
ARM64Reg::Q11, ARM64Reg::Q11,
ARM64Reg::Q12, ARM64Reg::Q12,
ARM64Reg::Q13,
// Caller saved // Caller saved
ARM64Reg::Q16, ARM64Reg::Q16,

5
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h
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@ -26,9 +26,8 @@ constexpr Arm64Gen::ARM64Reg PPC_REG = Arm64Gen::ARM64Reg::X29;
constexpr Arm64Gen::ARM64Reg DISPATCHER_PC = Arm64Gen::ARM64Reg::W26; constexpr Arm64Gen::ARM64Reg DISPATCHER_PC = Arm64Gen::ARM64Reg::W26;
// FPR constants // FPR constants
constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_0000_0000 = Arm64Gen::ARM64Reg::Q13; constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_0000_0000 = Arm64Gen::ARM64Reg::Q14;
constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_0000_0000_3F80_0000 = Arm64Gen::ARM64Reg::Q14; constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_FFF8_0000_3F80_0000 = Arm64Gen::ARM64Reg::Q15;
constexpr Arm64Gen::ARM64Reg FPR_CONSTANT_FFF8_0000_0000_0000 = Arm64Gen::ARM64Reg::Q15;
#ifdef __GNUC__ #ifdef __GNUC__
#define PPCSTATE_OFF(elem) \ #define PPCSTATE_OFF(elem) \

5
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -46,9 +46,8 @@ void JitArm64::GenerateAsm()
// Generate FPR constants // Generate FPR constants
m_float_emit.MOVI(8, EncodeRegToDouble(FPR_CONSTANT_0000_0000_0000_0000), 0); m_float_emit.MOVI(8, EncodeRegToDouble(FPR_CONSTANT_0000_0000_0000_0000), 0);
m_float_emit.FMOV(EncodeRegToSingle(FPR_CONSTANT_0000_0000_3F80_0000), 0x70); MOVI2R(ARM64Reg::X30, 0xFFF8'0000'3F80'0000ULL);
MOVI2R(ARM64Reg::X30, 0xFFF8'0000'0000'0000ULL); m_float_emit.FMOV(EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_3F80_0000), ARM64Reg::X30);
m_float_emit.FMOV(EncodeRegToDouble(FPR_CONSTANT_FFF8_0000_0000_0000), ARM64Reg::X30);
MOVP2R(PPC_REG, &m_ppc_state); MOVP2R(PPC_REG, &m_ppc_state);