There's no real requirement to make this const, and this should also
be decided by the calling code, considering we had places that would
simply cast away the const and carry on.
Migrates the state to be instance-based as opposed to being a flat
namespace. This keeps behavior localized to its own instantiable unit
(and forces uses of the class to also be localized, lest they cart around
an instance all over the place).
This was necessary to work around a FS timing issue which caused small
writes to take much longer than they should.
Now that we emulate timings for the FS module including its file cache,
we don't need to maintain this workaround anymore.
Everything that links in core doesn't need to see anything related to bochs, because it's only used internally.
Anything else that relies on bochs should be linking it in explicitly.
Using this in its current form would invoke undefined behavior, as it's
using a union to type pun between data types. It's also, well, unused,
so we don't need to keep it around.
We already read the necessary information with the
HostRead_Instruction() call. Internally, it calls HostRead_U32() as
well, so there's no difference in behavior.
If the locked cache isn't enabled, dcbz_l is illegal to execute
(locked cache is off, locked cache instructions don't work, makes sense)
This makes exception handling more accurate. It was previously possible to hit the DSI exception
handler when HID2[LCE] is set to zero, which isn't correct.
With this change we no longer hit the DSI handler, however we still have a lingering issue elsewhere
likely to do with exception precedence, we seem to hit the Floating Point exception handler instead
in some cases. This isn't due to the instruction itself directly however, so this is just another bug
to fix elsewhere.
This is one of the conditions for an alignment exception documented in
the 750CL architecture reference manual in section 4.5.6, which also
applies to the Gekko microprocessor.
This is an exception condition documented within section 4.5.6 in the
architecture reference manual for the PPC 750CL, which also applies to
the Gekko microprocessor.
Also moves dcbz_l's implementation out of Interpreter_Paired and beside
dcbz where it belongs.
The effective address given to these instructions must be word (4 byte) aligned,
and if the address is not aligned like that, then an alignment exception
gets triggered.
We currently don't update the DSISR in this case properly, since we
didn't really handle alignment exceptions outside of ecowx and eciwx,
and even then the handling of it isn't really that great, considering
the DAR isn't updated with the address that caused the exception to
occur.
The DSISR will eventually be amended to be properly updated.
