099e6c9ab6
docs/DSP: Trivial adjustment to BLOOP{,I} sub-operation order
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Noticed while tracing in a BLOOP using DSPSpy with $st{0..3} unmasked.
BLOOPI assumed to follow the pattern.
2022-09-30 11:07:41 +00:00
f47dfc3dba
docs/DSP: Update version and history
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The GFDL requires the history section to be updated.
2022-06-01 22:26:59 -07:00
24a339f437
docs/DSP: Explain 16-bit and 40-bit modes
2022-06-01 22:25:59 -07:00
d297ab18e6
docs/DSP: Add notes highlighting the difference between 'LS and 'SL
2022-06-01 22:25:59 -07:00
0dd181f461
docs/DSP: Add missing dollar signs in shift instruction operation sections
2022-05-31 16:26:55 -07:00
7c63bd1893
docs/DSP: Fix inconsistency with ADDI and CMPI
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We don't have anything called $amD, though we do have $acsD. However, these instructions affect flags based on the whole accumulator, so it's better to just use $acD.
2022-05-29 15:00:09 -07:00
4dc7208195
docs/DSP: Fix typo with arithmetic instructions that take a 16-bit immediate
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These instructions used an 'r' in their bit list, but a 'd' in the operands.
2022-05-29 15:00:09 -07:00
b349254ff4
docs/DSP: Document the behavior when main and extended opcodes both write to the same register (the write backlog)
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For more information, ApplyWriteBackLog, WriteToBackLog, and ZeroWriteBackLog were added in b787f5f8f7
and the explanatory comment was added in fd40513fed
, although it did not mention the specific instructions that could trigger this edge case. The statements about which registers can be written by main opcodes and extension opcodes are based on my own checking of all instructions in the manual.
2022-05-29 15:00:09 -07:00
bb01ba60d6
docs/DSP: Fix typo in 'NOP comment
2022-05-29 15:00:09 -07:00
83aabbbece
docs/DSP: Clarify LRS note
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$acS.h was a typo, which has been replaced with $acD.h.
2022-05-29 15:00:09 -07:00
ce4aba7d5e
docs/DSP: Rename CMPAR to CMPAXH
2022-05-27 18:22:38 -07:00
0531e51e39
docs/DSP: Fix "ILLR" typo in Instruction Memory section
2022-05-21 22:59:04 -07:00
534d92d2c5
Add tested bootloading transfer size
2022-05-14 23:12:53 -04:00
2906889804
Core: Add a Maker field for GameModDescriptors.
2022-01-02 06:06:53 +01:00
aa0595589a
docs: Add JSON Schema for game mod descriptors.
2021-12-12 21:26:09 +01:00
9de7ef6d8d
Fix improper naming
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I'm so sorry
2021-11-24 17:04:30 +01:00
b3d57eb25f
docs: Fix incorrect reference to wia_exception_t
2021-08-26 11:24:56 +02:00
44129dda4c
dsp_rom: Add version numbers and hashes to VerifyRoms and readme
2021-08-22 10:49:46 -07:00
a5e2a0d973
dsp_rom: Remove illegal use of AX with SRS
2021-08-22 10:49:46 -07:00
c881f4db22
dsp_rom: add pseudo code and fix small accuracy issues
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Doesn't fix anything, hence not upstreaming this.
2021-08-22 10:49:46 -07:00
d0b40528e5
dsp_rom: Fix readme eols and trailing whitespace
2021-08-22 10:49:46 -07:00
4fa9517ba3
docs/DSP: Update version and history
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The GFDL requires the history section to be updated.
2021-08-21 17:07:14 -07:00
9ef388f1c3
docs/DSP: NEG can set overflow and carry
2021-08-21 17:07:14 -07:00
602163b623
docs/DSP: Fix typo with MULCMVZ and MULCMV
2021-08-21 17:07:14 -07:00
c51c339424
docs/DSP: Document initialization process
2021-08-21 17:07:14 -07:00
5bf59f3ce4
docs/DSP: A failed RETcc only inceases PC by 1, not 2
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This is because RETcc is a single-word instruction.
2021-08-21 17:07:14 -07:00
1b84721b7f
docs/DSP: Add RTIcc
2021-08-21 17:07:14 -07:00
5611bd8f23
docs/DSP: Change conditional names to match Dolphin
2021-08-21 17:07:14 -07:00
af10eab938
docs/DSP: Split SRSH from SRS
2021-08-21 17:07:14 -07:00
408623b6e9
docs/DSP: Document behavior of LRS/SRS/SI with CR
2021-08-21 17:07:14 -07:00
8fa649e1d6
docs/DSP: Document masking/sign extension behavior of registers
2021-08-21 17:07:14 -07:00
7c645e1865
docs/DSP: Fix registers used by MOVAX and MOV
2021-08-21 17:07:14 -07:00
be753e5a45
docs/DSP: MADDC operates on acS.m, not acS.l
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This matches the prose and Dolphin's implementation.
2021-08-21 17:07:13 -07:00
0796fada17
docs/DSP: Add information about flags for every instruction
2021-08-21 17:07:13 -07:00
9249454f33
docs/DSP: Document overflow and carry behavior
2021-08-21 17:07:13 -07:00
a8ec0ad27f
docs/DSP: Fix MULXAC bytes
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The previous encoding was for MULXMVZ.
2021-08-21 16:05:06 -07:00
2db2683ea9
docs/DSP: Fix 'S format
2021-08-21 16:05:06 -07:00
139e05800f
docs/DSP: Fix 'LS encoding
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The old encoding was a copy of 'LN.
2021-08-21 16:05:06 -07:00
8767df40e5
docs/DSP: Fix acD/acR conflation in shift instructions
2021-08-21 16:05:06 -07:00
332bb6fd55
docs/DSP: Fix operation for LSR/ASR
2021-08-21 16:05:06 -07:00
2eb791d5e1
docs/DSP: Note that ADDAXL is unsigned
2021-08-21 16:05:06 -07:00
953670b057
docs/DSP: Fix operation of ADDR and SUBR
2021-08-21 16:05:06 -07:00
8881ecef19
docs/DSP: Adjust operation for CMPI and CMPIS
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This more clearly indicates what it is supposed to do.
2021-08-21 16:05:06 -07:00
79664d419c
docs/DSP: Document rounding behavior of CLRL
2021-08-21 16:05:06 -07:00
1bcea561e9
docs/DSP: Add 'NOP
2021-08-21 16:05:05 -07:00
29b61d463e
docs/DSP: Document 'LD and 'LDAX
2021-08-21 16:05:05 -07:00
031621bf51
docs/DSP: Document behavior and instructions when the first nybble is 3
2021-08-21 16:05:05 -07:00
211c2b5d99
docs/DSP: Add most missing instructions
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These instructions were already implememented by Dolphin, but never added to the manual. Extension instructions will be handled in a later commit, as wlil instructions that were not previously implememented by Dolphin.
2021-08-21 16:05:05 -07:00
446b1d2f13
docs/DSP: Adjust bit names in opcode table
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The old names did not match the ones used by the instructions themselves, and were generally fairly inconsistent.
2021-08-21 16:05:05 -07:00
16da6e214d
docs/DSP: Hyperlink opcode names
2021-08-21 16:05:03 -07:00