Sintendo
363f3f82bb
DSPJitRegCache: Simplify WriteReg
...
The intent here is to generate a more compact instruction if a 32-bit
immediate can be zero-extended to the desired 64-bit immediate.
Nowadays the emitter is smart enough to do this for us, so this logic is
redundant.
2020-08-05 10:23:28 +02:00
..
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