33 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
WRR	5eb103ad72	Fix SPI read to work after a reset, and add LCD peripheral register information.	2020-11-23 21:39:29 -05:00
WRR	2917980d3f	correct readme	2020-11-23 03:25:39 -05:00
WRR	e556638da6	Add a couple of test firmwares to control the display backlights.	2020-11-23 03:24:10 -05:00
WRR	8b300eb21a	More backlight info.	2020-11-23 01:17:57 -05:00
WRR	37d064b745	Add a bit more information to the readme.	2020-11-23 01:10:09 -05:00
WRR	ab0d626124	Add information about STM32H7B0 internal RAM banks.	2020-11-21 19:45:55 -05:00
WRR	20d2968934	Update the disassembler to place code at the likely base address of 0x90000000 (the usual QUADSPI memory-map location)	2020-11-20 21:40:39 -05:00
WRR	e4901f6ad1	Add a script to disassemble a file containing a Thumb hex dump.	2020-11-20 21:36:10 -05:00
WRR	07a4357b5b	Read the status register a few times to give the command time to take effect.	2020-11-20 20:26:50 -05:00
WRR	a29a1d26ab	Update software SPI program to read out portions of the SPI Flash memory.	2020-11-20 17:20:57 -05:00
WRR	a70b6891e6	Outline a software SPI program to interact with the on-board Flash memory.	2020-11-20 15:45:10 -05:00
WRR	c8548bbae6	Start working on a program to backup the SPI Flash image.	2020-11-20 01:21:39 -05:00
WRR	7773b4a784	Add Octo-SPI timing register value	2020-11-20 01:17:16 -05:00
WRR	26b4c1c486	Add link to the Flash chip's datasheet.	2020-11-20 00:14:37 -05:00
WRR	0e147948d3	Add more Quad-SPI Flash info	2020-11-19 23:21:25 -05:00
WRR	587939780d	Clarify input pull-up pins; they could be buttons, or interrupt inputs from external chips.	2020-11-19 23:02:02 -05:00
WRR	c4dd77a81b	Clarify OTYPER and pin mappings	2020-11-19 23:00:09 -05:00
WRR	bed7d11dd3	Update pin B4 alternate function	2020-11-19 22:45:59 -05:00
WRR	a1eb659d71	Add named definitions for the pin alternate function mappings.	2020-11-19 22:43:06 -05:00
WRR	7579d63faa	Add pin mapping table to the readme.	2020-11-19 22:27:50 -05:00
WRR	da4df1934b	Correct DTCMRAM region name in linker script	2020-11-19 22:03:51 -05:00
WRR	116b5621c9	Remove extraneous vector table rule from the Makefile	2020-11-19 22:03:07 -05:00
WRR	ce0e36dc68	Add OCTOSPI1 peripheral base address	2020-11-19 21:53:25 -05:00
WRR	14e443c3d5	Clarify the readme...	2020-11-19 21:48:06 -05:00
WRR	10ac227131	Merge branch 'main' of github.com:WRansohoff/game_and_watch_fun into main	2020-11-19 21:42:49 -05:00
WRR	743a8e26ff	Add a brief explanation of how to access the board's debug interface.	2020-11-19 21:42:41 -05:00
WRansohoff	9ee6be7b15	Fix register dump styling	2020-11-19 21:15:24 -05:00
WRR	a30bf41744	Add a basic readme.	2020-11-19 21:12:20 -05:00
WRR	50ec587c52	Add a minimal RAM program to run on the device without modifying its Flash memory.	2020-11-19 21:05:26 -05:00
WRR	1e016813ea	Add device header files for STM32H7B0xx chips.	2020-11-19 21:04:52 -05:00
WRR	3719986cc5	Add initial STM32H7B0VB linker script.	2020-11-19 21:04:26 -05:00
WRR	903040d8c8	Add OpenOCD configurations for convenience (normally located in /usr/share/openocd/scripts/)	2020-11-19 21:03:49 -05:00
WRR	c6559426aa	Add MIT license	2020-11-19 21:03:05 -05:00