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Added SuperCard Lite support
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@ -42,6 +42,9 @@
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2006-08-07 - Chishm
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* Moved the SD initialization to a common function
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2006-08-19 - Chishm
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* Added SuperCard Lite support
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*/
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#include "io_scsd.h"
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@ -54,10 +57,11 @@
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/* bit 0: command bit to read */
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/* bit 7: command bit to write */
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#define REG_SCSD_DATAWRITE (*(vu16*)(0x09000000))
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#define REG_SCSD_DATAREAD (*(vu16*)(0x09100000))
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#define REG_SCSD_DATAREAD_32 (*(vu32*)(0x09100000))
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#define REG_SCSD_LOCK (*(vu16*)(0x09FFFFFE))
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#define REG_SCSD_DATAWRITE (*(vu16*)(0x09000000))
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#define REG_SCSD_DATAREAD (*(vu16*)(0x09100000))
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#define REG_SCSD_DATAREAD_32 (*(vu32*)(0x09100000))
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#define REG_SCSD_LITE_ENABLE (*(vu16*)(0x09440000))
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#define REG_SCSD_LOCK (*(vu16*)(0x09FFFFFE))
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/* bit 0: 1 */
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/* bit 1: enable IO interface (SD,CF) */
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/* bit 2: enable R/W SDRAM access */
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@ -87,6 +91,10 @@ static inline void _SCSD_unlock (void) {
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_SC_changeMode (SC_MODE_MEDIA);
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}
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static inline void _SCSD_enable_lite (void) {
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REG_SCSD_LITE_ENABLE = 0;
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}
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static bool _SCSD_sendCommand (u8 command, u32 argument) {
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u8 databuff[6];
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u8 *tempDataPtr = databuff;
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@ -228,6 +236,8 @@ static bool _SCSD_readData (void* buffer) {
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volatile register u32 temp;
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int i;
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_SCSD_enable_lite();
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i = BUSY_WAIT_TIMEOUT;
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while ((REG_SCSD_DATAREAD & SCSD_STS_BUSY) && (--i));
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if (i == 0) {
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@ -329,6 +339,8 @@ bool _SCSD_writeSectors (u32 sector, u32 numSectors, const void* buffer) {
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int i;
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while (numSectors--) {
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_SCSD_enable_lite ();
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// Calculate the CRC16
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_SD_CRC16 ( data, BYTES_PER_READ, (u8*)crc);
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@ -32,6 +32,9 @@
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@ 2006-07-22 - Chishm
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@ * First release of stable code
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@
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@ 2006-08-19 - Chishm
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@ * Added SuperCard Lite support
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@
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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.align 4
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@ -86,10 +89,18 @@ _SCSD_writeData_data_loop_unaligned:
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@ Write the data to the card
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@ 4 halfwords are transmitted to the Supercard at once, for timing purposes
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@ Only the first halfword needs to contain data
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@ Only the first halfword needs to contain data for standard SuperCards
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@ For the SuperCard Lite, the data is split into 4 nibbles, one per halfword
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_SCSD_writeData_data_loop:
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ldrh r3, [r0], #2
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@ This bit added for SCLite. Notice that the shift is not the same as in
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@ the original (buggy) code supplied by Romman
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add r3, r3, r3, lsl #20
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mov r4, r3, lsr #8
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stmia r2, {r3-r4}
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subs r5, r5, #2
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bne _SCSD_writeData_data_loop
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